logic to memory mapping

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

logic to memory mapping

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Hi,

I am trying to use the mapping constraint "logic to memory mapping" and tried to synthesize several designs with and without the above mentioned mapping constraint. The benchmarks I have used include c432 (27-channel interrupt controller), c1355 (32-bit Single Error Correcting circuit), c1908 (16-bit Single Error Correcting and double error detecting circuit) and c3540 (8-bit ALU). I also tried out a 8-tap FIR filter, all in Stratix IV series of devices.

Problem is I don't see any logic being mapped to memory for improving density. Can you please guide me on the effective usage of logic to memory mapping and where (in what benchmarks or operation node types) exactly can such mapping constraints be helpful.

Thanks

Anandaroop Ghosh

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