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We are using Cyclone V SOC along with Quartus Prime Standard Edition, and we would like to the know the delay involved for the input pin/signal (asynchronous) to propagate through the fpga/soc die without getting clocked in (not synchronized using sync registers) and come out via an output pin of the same fpga/soc.
How much would the delay be in this case?
We are seeing close to 12 ns in our case, is this real or are we doing something wrong?
What all factors contribute to this delay? Like input buffer delay for input pin/port, output buffer delay for output pin/port, internal propagation/routing delay, what else?
Why do I need answer to this question: I know you are thinking why we would not clock in (synchronous) the incoming async signal, we plan on doing this eventually but for now we are just trying to understand what is happening in our design for debugging an issue.
thanks in advance
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Doesn't sound out of the realm of possibility depending on the pins and route selected. Are you measuring the 12ns directly or using the timing analyzer in Quartus?
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Are you using the timing analyzer to measure the 12ns delay?
Regards,
Richard Tan
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We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.
If you have any further questions or concerns, please don't hesitate to let us know.
Thank you for reaching out to us!
Best Regards,
Richard Tan

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