Hi Folks,I want to implement a delay line in my Cyclone 3 FPGA. Therefore I wrote the following a process in VHDL file:
BEGIN IF (rising_edge(CLK)) THEN temp_sign_in <= INPUT; END IF; temp_sign_4 <= temp_sign_in AND (NOT SHORT_DELAY) AND (NOT LONG_DELAY); temp_sign_1 <= temp_sign_in; temp_sign_5 <= temp_sign_1 AND SHORT_DELAY; temp_sign_2 <= temp_sign_1; temp_sign_6 <= temp_sign_2 AND LONG_DELAY; OUTPUT <= NOT (temp_sign_4 OR temp_sign_5 OR temp_sign_6); END PROCESS;At first, the input signal will be reclocked, and after that the signal is forked into 3 AND-branches, that will all have an increased delay. In the end, the signal will be joined by an OR-gate to the output. To prevent the Altera Sythesis to delete those redundant traces, I decleared the signals as follows: --- Quote Start --- SIGNAL temp_sign_in: std_logic; SIGNAL temp_sign_1: std_logic; SIGNAL temp_sign_2: std_logic; SIGNAL temp_sign_3: std_logic; SIGNAL temp_sign_4: std_logic; SIGNAL temp_sign_5: std_logic; SIGNAL temp_sign_6: std_logic; attribute syn_keep: boolean; attribute syn_keep of temp_sign_in: signal is true; attribute syn_keep of temp_sign_1: signal is true; attribute syn_keep of temp_sign_2: signal is true; attribute syn_keep of temp_sign_3: signal is true; attribute syn_keep of temp_sign_4: signal is true; attribute syn_keep of temp_sign_5: signal is true; attribute syn_keep of temp_sign_6: signal is true; --- Quote End --- Actually this works quite fine, all the signals are kept as I can see form the Technology Map Viewer. Unfortunately, the Synthesis adds some logic inbetween the delay registers (actually this logic lies in the overlying VHDL-code, so I guess the sythesis wants to save space). What I don't want. I tried to use the LogicLock-Option on my VHDL-File. In the Chip Planner the Cells aren't moved, but it doesn't prevent the Synthesis to alter my LUTs. Now my question: Is there another way what I can do to protect the structure I want to have? Thank you for any comment!
i would try incremental compile and maybe an imported post-fit .qxp file. create a new project with your delay HDL, fit it, and export as a post-fit netlist. you could even put it in a logic lock. then import the .qxp into your top level project and preserve fit information, it shouldn't try to reoptimizei'd be interested in the results if you try it
I just want to ask why? trying to align signals like this is never going to work reliably. secondly: why have you got all the combinatorial logic in a process?
Dear pancake, thank you for your hint. I have implemented it in the way you mentioned. Now the Synthesis and the Fitter are leaving this part of the FPGA untouched. Thanks for your advice!@ Tricky: I actually don't want to align signals. Since there are some HF-signals on my board (32 times the clock frequency of the FPGA), for some frequency-bands the setup/hold times of some D-latches aren't kept. To prevent this, I am inserting an additional delay. Everything works fine now. Sorry for my VHDL coding style, i'm relatively new to FPGAs.
Im still concerned that you are trying to manually fudge something. The problem with fudging delays is that while they may work at room temp, as the board heats up or cools the delay can change, so you then violate your setup and hold times again, and it's going to happen without much warning and could easily be intermittent.
Thank you Tricky for telling me your concerns.You are right, my delay line settings are only valid when the board is at a specific temperature. However, I don't consider this as a problem.