Demultiplexer with latched value

Altera_Forum · ‎08-04-2009

I am using a demultiplexer with six output registers. The code is pretty simple.

 process(X,sel)
  begin
  case sel is
   when "000"=> 
    A <=X; 
   when "001" => 
    B <=X; 
   when "010" =>
    C <=X; 
   when "011" =>
    D <= X;
   when "100" =>
    E <= X;
   when "101" =>
    F <= X;
   when others =>null;
end case;
end process;

I do not reset output regisers since I want to preserve them. That is why I get the following warnings.

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Warning (10631): VHDL Process Statement warning at demux.vhd(21): inferring latch(es) for signal or variable "C", which holds its previous value in one or more paths through the process

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Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

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Why is wrong to have latched output registers?

What do I need to do to remove them?

Altera_Forum · ‎08-04-2009

Hi,

Have a read of http://www.altera.com/literature/hb/qts/qts_qii51007.pdf page 42 it explains why latches are a bad idea. In short FPGAs are built out of storage elements that are all connected to a common clock.

Altera_Forum · ‎08-04-2009

Thanks Uk Fixer. I found a solution added a clock to sensitivity list.

Altera_Forum · ‎08-05-2009

In fact, demultiplexers aren't often used. Instead, a decoder providing clock-enable signals is preferred.

Nevertheless, your VHDL code must assign every signal in order to avoid parasite latches.


process(X,sel)
  begin
  case sel is
   when "000"=> 
    A<=X; 
    B<=(others=>'0');
    C<=(others=>'0');
    D<=(others=>'0');
    E<=(others=>'0');
    F<=(others=>'0');
   when "001" => 
    A<=(others=>'0');
    B<=X;     
    C<=(others=>'0');
    D<=(others=>'0');
    E<=(others=>'0');
    F<=(others=>'0');
   when "010" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=X;         
    D<=(others=>'0');
    E<=(others=>'0');
    F<=(others=>'0');
   when "011" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=(others=>'0');
    D<=X;             
    E<=(others=>'0');
    F<=(others=>'0');
   when "100" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=(others=>'0');
    D<=(others=>'0');
    E<=X;                 
    F<=(others=>'0');
   when "101" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=(others=>'0');
    D<=(others=>'0');    
    E<=(others=>'0');
    F<=X;                 
end case;
end process;

Altera_Forum · ‎08-05-2009

parrado wrote:

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your VHDL code must assign every signal in order to avoid parasite latches

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It does not have to. As I wrote , I needed to retain the values on each itteration of next register being sent to output.

that is why , i could not issue statements such as

B<=(others=>'0');

It would reset tha value of corresponding output pins to zero, which I don't want.

Thanks

Altera_Forum · ‎08-06-2009

Yeah, you have used the first approach.

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Instead, a decoder providing clock-enable signals is preferred.

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