LVDS and Cyclone II Nios DEV Kit

[Altera_Forum]

Hello, 

 Currently I use Nios II development kit with EP2c35 device. Also this kit contains Prototype connectors (Proto1 and Proto2).  Can I use some I/O pins of this connectors as differential pairs (LVDS)? If yes, If it is just enough to select in the Quartus II Pin Planner which pins are differential pairs by setting LVDS standard, or I have to do some additional settings and add modules (buffers?)?   Thank you very much in advance. U.

[Altera_Forum]

The EP2C35 Nios II board as shipped has no I/Os suited for LVDS usage. The proto and PMC expansions signals have level converters for 5 V tolerance and are fixed to 3.3V VCCIO. Only the mictor connector signals are basically prepared to be used for LVDS. But VCCIO8 has to be changed to 2.5V by a solder jumper, also termination resistors must be possibly added to the board. See the board schematic for details.

[Altera_Forum]

FvM, 

Thank you very much for the response. I've got more additional questions very important for me. I have a core, this is a master of a 4-bit wide bus ( Pclk, synch, TX, RX). PCLK is 8MHz. I want to use Cyclone II I/O LVDS differential mode for them. Is it just enough to set LVDS standard in the appropriate column of the Pin Planner or I should use special primitives? Is there some application notes with examples how to use LVDS signalling with ALtera FPGA.   And the second question, what blocks can I use if TX should be tri-stated? It’s used to allow the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention.   Thank you.

[Altera_Forum]

Typically, LVDS I/O is used in combination with the SERDES (ALTLVDS) MegaFunction. If you only need LVDS receivers and transmitters for general I/O, nothing must be done except assigning an LVDS I/O standard to the pin. 

 Bidirectional LVDS is supported beginning with Cyclone III and Stratix III, but not available for Cyclone II, see the ALTIOBUF MegaFunction and AN522. With Cyclone II, two pin pairs would be needed to implement a similar function, one LVDS receiver pair and a pair of pseudo-differential operated tris-state buffers.  If you only need a tri-state differential driver, it's more easy.

[Altera_Forum]

Thank you again, 

 The RX signal, a data from slaves, should be differential and tri-stated by OE signal generated by the master located in FPGA.    Can you suggest how to do "one LVDS receiver pair and a pair of pseudo-differential operated tris-state buffers" practically?   I'm very greatful for your support,   U.

[Altera_Forum]

I understand, that only need tri-state LVDS drivers, but not bidirectional ones. So the point is to use pseudo-differential drivers. This simply means, you have two pins, one is driven by the positive and one by the negative (inverted) signal, both use a common tri-state signal. The solution won't work at high LVDS speeds and series resistors should be provided, if a correct LVDS differential voltage level is intended.

[Altera_Forum]

Great! 

Understand.:)  Thank you very much.