Details about how to instantiate sdram controller module

[Altera_Forum]

Hi guys. 

first I will mention that I tried to read and understand :"external memory interface handbook volume 2", and the questions are things that im still not understanding and need your help.  Im using MAX10 FPGA , and quartus 2.  Im trying to instantiate sdram controller to my project so Im first learning how to do it, by opening a new project.   So, those are the steps I did, and the questions I have about them: 1.ip extraction:from "ip catalog" I extracted "DDR2 SDRAM controller with uniphy".  2.atttaching files:From the files that were extracted I took the the project the qip file, which attached all the files.  q:Do I need all of those files? files like:"sdram_interface_s0.v", "sdram_interface_c0.v","alt_mem_ddrx_input_if.v" . And Ill be happy to know what are all of those files? are they the "Inside" of the controller ?? and all I have to deal with is :"Sdram_interface.v" file??  3.pin assignments: I used the tcl script that I got from the extracted ip files.  q: Do I need anymore assignments to do?  4.instantiating the module: I instantiate this way:    sdram_interface(  .pll_ref_clk(clk), // in pll_ref_clk.clk  .global_reset_n(), // in global_reset.reset_n  .soft_reset_n(), // in soft_reset.reset_n  .afi_clk(clk), // afi_clk.clk  .afi_half_clk(), // afi_half_clk.clk  .afi_reset_n(), // afi_reset.reset_n  .afi_reset_export_n(), // afi_reset_export.reset_n  .mem_a(mema), // out memory.mem_a  .mem_ba(memba), // out .mem_ba  .mem_ck(mem_clk), // .mem_ck  .mem_ck_n(), // .mem_ck_n  .mem_cke(mem_cke), // out .mem_cke  .mem_cs_n(), // .mem_cs_n  .mem_dm(), // .mem_dm  .mem_ras_n(), // .mem_ras_n  .mem_cas_n(), // .mem_cas_n  .mem_we_n(), // .mem_we_n  .mem_dq(), // .mem_dq  .mem_dqs(), // .mem_dqs  .mem_dqs_n(), // .mem_dqs_n  .mem_odt(), // .mem_odt  .avl_ready(avl_ready), // avl.waitrequest_n  .avl_burstbegin(avl_burstbegin), // in .beginbursttransfer  .avl_addr(avl_addr), // in .address  .avl_rdata_valid(avl_rdata_valid), // out .readdatavalid  .avl_rdata(avl_rdata), // out .readdata  .avl_wdata(), // in .writedata  .avl_be(), // in .byteenable  .avl_read_req(avl_burstbegin), // in .read  .avl_write_req(1'b0), // in .write  .avl_size(2'b10), // in .burstcount  .local_init_done(), // status.local_init_done  .local_cal_success(), // .local_cal_success  .local_cal_fail() // .local_cal_fail  ); Im still trying to learn what each port do, so I did only the one I know and they are important.    5.wrote to the memory: I wrote to the memory using de-control panel ,and I want to check, and see if I can do a read transaction. Q: I dont really know how to do that.. I thought about doing a test bench for the file that instantiating the sdram controller module,but it doesnt make any since. what am i missing??!!? Im feeling like I missing a big piece here, and Ill be happy for your help.  Thanks a lot!!!

[Altera_Forum]

Hi, 

   --- Quote Start ---  Im trying to instantiate sdram controller to my project so Im first learning how to do it, by opening a new project.  --- Quote End ---    Refer “Implementing and Parameterizing Memory IP” from external memory interface handbook volume 2 & using following links generate (.v or .vhd) files.  https://www.youtube.com/watch?v=yeh2bk9pup8 http://www.altera.com/education/training/courses/omem1110    --- Quote Start ---  Do I need all of those files? files like:"sdram_interface_s0.v", "sdram_interface_c0.v","alt_mem_ddrx_input_if.v" . And Ill be happy to know what are all of those files? are they the "Inside" of the controller ?? and all I have to deal with is :"Sdram_interface.v" file??   --- Quote End ---    Yes, these are sequencer file, controller core file, memory interface file generated during “Generate Example Design”, you should deal with “Sdram_interface.v” file & instantiate this module in your project with instance name & keep all related files at one location & add them to your project when required.     --- Quote Start ---   Do I need anymore assignments to do?   --- Quote End ---   It depends upon your Top module in project.    --- Quote Start ---  5.wrote to the memory:[/B][/U] I wrote to the memory using de-control panel ,and I want to check, and see if I can do a read transaction. Q: I dont really know how to do that.. I thought about doing a test bench for the file that instantiating the sdram controller module,but it doesnt make any since.  --- Quote End ---   To check read,write and for debug you can use signal tap.   Best Regards Vikas Jathar  Intel Customer Support – Engineering (Under Contract to Intel)