Difference among Qsys Sim model, test-bench Qsys sys and test-bench Sim model

[Altera_Forum]

I'm confused about the purposes of different models that are offered during the generation process. In 'Generation' window you can have: 

1) Simulation model 2) Test-bench Qsys system 3) Test-bench simulation model 4) Synthesis files (which I understand its purpose)  My understanding is that (2) is a wrapper system that contains the Qsys system to be tested, it also contains BFMs that are connected to the top-level interfaces of the system to be tested. By writing another HDL file that drives the top-level interfaces, I can check the behaviour of the system.  Q1: If the above is correct, now I want to do that in ModelSim, my guess is that having (2) alone is not enough, I also need (3) so that (2) can be simulated in ModelSim, is that correct?  Q2: If my guess in Q1 is correct, then in what situation I may want to generate (2) alone without generating (3)? (I think this is explained in "Qsys System Design Tutorial" but I didn't quite follow it..)  Q3: Is (1) a subset of (2)+(3)? My understanding is that (2)+(3) = (1)+(BFMs simulation model), is that correct?  Q4: If I just want to test/simulate my Qsys system using standard BFMs in ModelSim, it is OK to unclick (1) and only use (2)+(3), is that correct?

[Altera_Forum]

Your question is a little difficult to answer without knowing what sort of components you have added to your Qsys system. 

 Click on each of the options and look at the code generated.  Typically I just generate a simulation model (in VHDL or Verilog depending on what I am doing).  I then explicitly add BFMs or device models for testing.  For example, when testing Avalon-MM slave components, I explicitly add an Avalon-MM master BFM to the design, eg., take a look at this tutorial;  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  In this thread (post# 25)  http://www.alteraforum.com/forum/showthread.php?t=32952&page=3  I show how to use the master and slave BFM.  I've also used the Qsys "Example Design" to get an idea of how to connect the DDR3 controller to a DDR3 model, and then rather than using that code, re-written a testbench in the style that I like.  The key to understanding Qsys generated code is to read it as "example" code. If you do not like it, then its ok not to use it :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Your question is a little difficult to answer without knowing what sort of components you have added to your Qsys system.  Click on each of the options and look at the code generated.  Typically I just generate a simulation model (in VHDL or Verilog depending on what I am doing).  I then explicitly add BFMs or device models for testing.  For example, when testing Avalon-MM slave components, I explicitly add an Avalon-MM master BFM to the design, eg., take a look at this tutorial;   --- Quote End ---    Thanks Dave,   So basically if I chose to generate test-bench qsys system and test-bench simulation model, the tool would generate a wrapper system containing an instance of DUT and another instance of BFMs, however if I did your way, DUT and BFMs would be within a single instance (BFMs are now virtually a part of DUT), a simulation model of such a single instance is equivalent to the simulation model of the wrapper system right?

[Altera_Forum]

--- Quote Start ---   So basically if I chose to generate test-bench qsys system and test-bench simulation model, the tool would generate a wrapper system containing an instance of DUT and another instance of BFMs   --- Quote End ---   Right, but the caveat is that the BFMs are attached to the "external" interfaces of the Qsys system, whereas most times you would want an Avalon-MM master BFM as part of the Qsys system, otherwise how can you exercise your system?    --- Quote Start ---   however if I did your way, DUT and BFMs would be within a single instance (BFMs are now virtually a part of DUT), a simulation model of such a single instance is equivalent to the simulation model of the wrapper system right?  --- Quote End ---   Not quite. My method is a mixture. I add an Avalon-MM BFM to the Qsys system, so that I can read/write the Avalon-MM slaves at whatever addresses that BFM master is connected to (typically the same address map as another master), and then I create a testbench with an instance of the Qsys system, and then add BFMs manually to that testbench, eg., a DDR3 memory model.  For testing Avalon-MM slave I/Os, I just test the state of the signals in the testbench stimulus process, and don't bother with BFMs.  Cheers, Dave

[Altera_Forum]

I see. Thanks a lot!