Hi,I have a PCIe in Gen3 x4 mode configured as a root port. I have 2 options for Gen3 x4. 128 bit 250 MHz or 256 bit 125 MHz. What is the difference between the two? I have looked into the files generated by Quartus and the files are entirely different for both of them. I was of idea that the efficiency and other factors remain the same. But I have a difference in internal architecture because of the increase in data width. So I want to know what are all the changes in them. Thanks, Vijey
This should be more a question of what do you need. Faster clock will be harder to place and route, but the wide bus will likely need more resources in your processing pipeline.
Both can be taken care in my FPGA. Question is when the data path has changed and it is changing architecture(i assume as the files are totally different), there will be some change in the performance also.In short, when I change my data path width to 256 bit, what all are changed? I want a 256 bit data path but my PCIe is unable to boot with it. In my 128 bit 250 MHz, my kernel boots and SSD is detected.