Hello! I'm attempt to simulate my quartus Prime 17 project..Project is simply 2 blocks for frame coding/decoding (already well simulated..) plus a Transceiver PHY block.. (no controller, I use PHY in a fixed mode, no reconfiguration needed) Quartus performs all Analysis & Sint fine! All IPs are generated correctly, with vhdl simulation options checked But, when I start automatically Modelsim Altera simulation tool, it fails attempting to execute vlog command in tcl file, reporting (vlog-2726) Config alt_sld_fab_alt_sld_fab_170_gtjio5q_cfg failed to access library 'name lib' All these lib files and directories exists! I havent' any problems generating files for simulation from Qsys/Transceiver component.. I cannot solve this issue, that stops my simulation test bench... Have you never find similar issues? Thanks!
Hi,Try simulating sample project. To debug http://www.alterawiki.com/wiki/cyclone_v_transceiver_phy_basic_design_examples Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
thanks for tip! I found the problem, due to my wrong strategy creating new project! I make a copy of an QSYS IP, but this is not correct. All IPs must be Re-generated starting from QSYS entry! ... Now Modelsim works fine!