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19680 Discussions

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Parkavi
Novice
351 Views

Hi,

 

I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopbacked to the same board and data from the fibre is getting deframed and send it to UART again. 

 

I programmed FPGA using memory(JIC file, SOF is converted to JIC for memory configuration).I loaded my code into flash it was working fine .If i power off my board, the output is null with the same working code. But it's happening occasionally on the  power sequence. Any help on this!!!!

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9 Replies
NurAiman_M_Intel
Employee
311 Views

Hi,


Have you follow the userguide for Transceiver PHY IP Core and Cyclone V userguide? After following this, you face the problem?


https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01080-1.7.pd...


https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf


Regards,

Aiman


Parkavi
Novice
304 Views

Hi sir,

 

Thank you for your response. i am new to this Transceiver Native IP. Yes we had done the configuration based on these documents only and with this we are able to get the right data most of the times during power cycles. Occasionally we see there is null data during such power cycle. Any suggestion on what could be the cause for such occasional erratic behavior? Which configuration of IP need to be relooked in this case? Please advice.

 

Thank you!!

NurAiman_M_Intel
Employee
300 Views

Hi,


What is the Quartus version that was use? Can you try with the latest Quartus version?

Also what do you mean by null data? Any error shown? Please provide a screenshot.


Regards,

Aiman


Parkavi
Novice
292 Views

Hi sir,

 

We are using Quartus-lite edition 20.1.Please find attached screenshot of output data packet details.

 

Thank you!!! 

NurAiman_M_Intel
Employee
261 Views

Hi,


  1. Can you try to program by using the latest version of Quartus lite which is 21.1 to see if you get the same problem?
  2. Also, please try to create a simple design, convert into JIC and then program it. Then try to power cycle. Do you get the same problem?


Regards,

Aiman



Parkavi
Novice
245 Views

Hi sir,

 

Will test those cases and let you know the observation.

Thank you!!

Parkavi
Novice
232 Views

Hi sir,

 

1.Tried with new quartus version but issue is not fixed.

2.The design without IP(transceiver native phy) is working fine on power cycle. But only with IP we are facing this problem. Even with IP,RX word aligner mode is in sync_sm mode, we didn't face this kind of issue but we faced data corruption in that mode. So we tried to use bitslip mode ,there is no data corruption but this null issue is occurring occasionally on power cycle.

Please guide us to move forward!!!

Thank you!!

Parkavi
Novice
174 Views

Hi Aiman,

 

My problem got resolved.

1. In manual word aligner mode, i manually drive rx_walign port when i sent word align pattern. In this case ,the above null issue was resolved.

2.As i said before, in sync_sm mode i found corruption in data packets. That was resolved by setting rx word align pattern as 17C in IP configuration , enabled 8b/10b encoder and decoder ,driving tx_datak port from rx_syncstatus  which is inverted and given.And transmitting BC to IP.

 

Thank you for your support!!!!

NurAiman_M_Intel
Employee
142 Views

I’m glad that your question has been addressed. Thank you for sharing your solution with the community. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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