CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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I want to interface my FPGA to a DAC using LVDS Standard. The problem is, that the FPGA and DAC pins topologies are not the same. Each FPGA positive pin cannot be directly (physically) connected to the corresponding DAC positive pin without using vias , something that is forbidden as the data rate is 400 Msps. I have attached a picture for you to see. Is there a way I can turn positive LVDS pins into negative ones and vice versa using Quartus? Would adding not gates be sufficient or will this cause functional and/or timing problems to the design? thanks Lambros
It's possible that you come across some issues which may require a bit of care but nothing serious. For example, you can't invert the output of altddio_out block -- your have to to invert the inputs.
It's not exactly forbidden to use vias for a 400 MBps connection, you can use them even for GBit interfaces. Typically, longer differential traces are run in a screened inner layer, so you have at least a pair of vias at each end. They can be used to invert the polarity as well. But I agree, that you should avoid vias if possible. If you have only a short connection on the top layer, I would also invert the driving nets inside the FPGA, as rbugalho sugested.
