Direct Link Interconnect

[jeddeame]

“ Intel® Agilex™ Logic Array Blocks and Adaptive Logic Modules User Guide “

Section “ 3.1.2. Local and Direct Link Interconnects “

There is no description of the Direct Link Interconnects.  Are there any Direct Link Interconnects in the Agilex architecture???

Can you provide any further detail?

[lixy]

Hi,

May I ask which "Agilex Architecture" You are referring to? Do you mean Hyperflex Core Architecture, or tile's building blocks?

You can understand what the Local and Direct Interconnects are through the Figure 3 on Page 7.

As described in 3.1.2, among the ALM outputs, some of them can drive the LAB inputs directly, which are Direct Interconnects. Local Interconnects are marked in "Figure 3", they drives the inputs of these ten ALMs within this LAB.

The Row/Column Interconnects refers to the general routing resource.

Regards,

Xiaoyan

[jeddeame]

We are using Agilex 7.  The picture looks like it was copied from the Stratix manual.  I am concerned this feature is not in Agilex

because section 3.1.2  says "any connection to a different row or column must use at least one general-purpose routing wire".  We don't want to use routing resources for speed.

Can you please answer:

==> Does Agilex 7 have Direct Link Interconnects ?????

Yes or No Please.

Thanks.

[lixy · Accepted solution]

Hi,

The architecture of Agilex LAB is similar to Stratix 10, and the answer is Yes, there is direct connection between labs.

Would you mind tell me why do you want to know?

Thanks & Regards,

Xiaoyan

[jeddeame]

Thanks.  Direct Connection is faster than through the routing fabric.