Divide two 36 Bit values

[Altera_Forum]

Hello,  

 i have a problem. I have to divide two 36 Bit Values, but i can't find a right design in Vhdl, which can do it. All the moduls can divide up to 32 bit, but no more. It should be synthesizable.  I need the quotient and the rest. Can anyone help me? The input type's of my entity are two std_logic_vector(35 downto 0) which i would convert in unsigned values (of the package "ieee.numeric_std.all") with the same length.   And this values, i have to divide. The dividend is the bigest value, so that the result's are only positive.   Thank's a lot,   phot

[Altera_Forum]

The LPM Divide megafunction will go up to 64 bits for both the numerator and denominator: 

 http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf

[Altera_Forum]

Thank's a lot for the fast answer.  

 Is there also a seperate module (entity) and not a function?

[Altera_Forum]

It is a module.

[Altera_Forum]

A divide function is not appropriate as it does now allow pipelining (unless your clock speed is about 2 MHz). The LPM_Divide is a module that is fully pipelined.

[Altera_Forum]

If you use the divide function and put a chain of flip flops after the division and use the value from the end of the chain for the output you might get lucky and Quartus will retime those registers (if you enable it) and shove them into the division logic. That said I would just use the megafunction or build your own if you want something custom.