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I am using Cyclone 10 GX device. The reference clock differential pins are set to be LVDS standard. I hope to use AC coupling and on-chip RD termination. If the pins have an internal DC bias voltage, I will not need to implement on-board bias network.
Thanks.
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Hello,
Cyclone 10 GX does not have internal DC bias voltage. You can refer for both of these link as you reference for your design.
1. Cyclone 10 GX Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf
2. Cyclone 10 GX GPIO: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
Thank you.
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Hello,
Cyclone 10 GX does not have internal DC bias voltage. You can refer for both of these link as you reference for your design.
1. Cyclone 10 GX Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf
2. Cyclone 10 GX GPIO: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
Thank you.
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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