Most microcontrollers have some kind hard-reset pin, for example nRST. Basically if you pull the pin low, the device completely resets.
This pin is often used for some kind of external POR or pushbutton reset.
Does the Cyclone 10 GX have something like this? The closest thing I could find was the DEV_CLRn pin. However, based on the description I'm not quite sure what it is saying. It seems like you first need to enable it in the device config, and then the description just doesn't seem like a normal nRST.
It says "Cyclone 10 GX devices support an optional chip-wide reset that enables you to
override all clears on all device registers, including the registers of the memory blocks
(but not the memory contents itself)." So the memory is not cleared? Will the FPGA go back into the configuration phase when the DEV_CLRn goes back high?
I'm not quite sure this behaves like what I need. I basically need to add an external POR for the FPGA and I don't know the best way to do this.
Thank you for reaching out to Intel FPGA Community.
Apologies for the delay. Would you clarify do you planning to reset all the IP or just LVDS/GPIO IP?
Thanks for following up.
I was able to make some changes in the surrounding schematic making it so that I wouldn't need this feature.
I was thinking complete device reset, so that it would have to read its configuration all over and everything. I did see the nCONFIG pin which seems like it might do what I wanted, but the documentation seems to indicate the use is if you need to load a different configuration into the device, rather than the intention being a complete device reset.
Alright, I will take note on that. If in future you would like to use the hard reset pin, I would say the nCONFIG pin is the most accurate pin for you. It is a dedicated configuration control input pin where pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level initiates reconfiguration.