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Downloading Error when both 3V I/O & tranceivers are used in a project

Shark121
Novice
299 Views

Hello,

 

I use a Avst-PCIe IP in my project, which has a 3V I/O pin for reset, and tranceivers's pin assignments for tx/rx channels. After compilation, I downloaded the .sof file into device use Quartus Programmer 20.2, and got the following errors:

Error(18950): Device has stopped receiving configuration data

Error(18948): Error message received from device: Device is in configuration state.

Error(209012): Operation failed

 

I searched the community, and found the following problem is very similar with my,

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Power-up-the-VCCR-GXB-and-VCCH-GXB-rails...

but I checked the VCCR/VCCT/VCCH power supply, which are all OK.

 

So, is there any other possible solution?Thank you!

0 Kudos
10 Replies
JohnT_Intel
Employee
250 Views

Hi,


Can you try to update your Quartus to 20.4? You may refer to https://www.intel.la/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/... for more information


Shark121
Novice
236 Views

Hi,

 

Thanks for your answer!

I update Quartus to the lates 21.1, but it doesn't work, the appearance is same.

Btw, my device is Stratix 10(1SX280 series).

 

So, is there any other possible solutions? Thank you !

JohnT_Intel
Employee
210 Views

Hi,


May I know if you are using embedded USB-blaster II? Have you try to reduce the TCK frequency? How many device is in the chain?


Shark121
Novice
207 Views

Hi,

 

Thank you for reply!

I'm using USB-blaster, not USB-blaster II.

I replace the OSC from 24MHz to 6MHz in the USB-blaster, the TCK frequency slowed, but my problem is still there.

Only one device in this downloading chain.

 

Expecting for your reply!

JohnT_Intel
Employee
206 Views

Hi,


Have you try other simple design? May I know if your refclk is running?


Shark121
Novice
202 Views

Hi:

 

Yes, the refclk is running. I make a mini-system design to download, it works.

This design only include three IPs(release_reset, clock, PLL), and some very simple logics(a counter connecting to a GPIO to drive a LED, to make a breathing lamp). This design can be downloaded and worked correctly.

I also make a design with instantiation of xcvr & 3V I/O seperately, with the same constrains of PCIe mentioned above, this design can also be downloaded, so it looks like only when the tranceiver & 3V I/O have internal relationshaips with each other, can trigger this problem.

JohnT_Intel
Employee
201 Views

Hi,


May I know if all the refclk used for the Transceiver is working and in correct clk? The reason is that I suspect that the refclk is not working correctly which cause the configuration to failed.


Shark121
Novice
181 Views

Hi,

 

I checked the global refclk is working correctly(25MHz), otherwise, the mini-system won't work.

In my design, PCIe module is uesed as EP(end point), and working clk is provided by the Host(root complex, in my system it's PC). This clk is assigned to the dedicated pin for PCIe Hard IP, but it's floated(not connected) when downloading. So, does it matter?

 

Two more clks(both are 156.25MHz) connect to the tranceiver, but not used for PCIe, designed to use for other two high-speed transmition.

One is connected to the same group of tranceivers with PCIe, but not the same bank(PCIe used bank 1K,1L, 156.25MHz used for 1N,1M), the other clk connected to the other group of tranceivers.

JohnT_Intel
Employee
176 Views

Hi,


Could you use the SDM Toolkit to check the configuration status after the JTAG configuration failure? You may follow the guide in Chapter 7.4.1 of https://www.intel.com/content/www/us/en/programmable/documentation/sss1439972793861.html.


Shark121
Novice
142 Views

Hi,

 

My problem solved!!

The key reason is the PCIe refclk not connected when dowloading. After cables connected between RC & EP, the program could be downloaded correctly. But when I used Cyclone V in my previous project, it's no need to connect cables between RC & EP when downloading program to FPGA, btw, it's Gen 1 of PCIe at that time, so is it new feature for S10 devices or Gen3 of PCIe?

 

Two more questions :

1. It looks like the refclk of RC must be stable when downloading the program of EP, what's the timing requirements, eg. how long should the refclk be stable after PoR?

2. In AS x4  booting mode, I drive low the "nConfig" pin to reboot the FPGA, after 3 times, it crashed, no data transfer between FPGA & flash. is that correct? or my usage is wrong? 

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