An error during schematic capture resulted in external clock oscilator being connected to pin IO_2_32/PLL_L_CLKOUT instead of to one of the CLKx_p/n signals.
I tried to instantiate a pll to convert 20MHz to 100MHz but fitter complains about the input pin.
I then tried to insert a clkcontrol IP between the pin and the PLL but still I get errors.
Errors from above test:
Error (176554): Can't place PLL "pll_20m_100m:U_1|altpll:altpll_component|pll_20M_100M_altpll:auto_generated|pll1" -- I/O pin CLK_20M (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device
The pin can obviously somehow get connected to the GCLK network, since it clocks the whole design under the case where I do not insert the pll. Is it possible to force this connection to GCLK and then give the GCLK as input to PLL?
To change the pin on the hardware will be problematic and a major pain in the A, hence I am trying to avoid it.
Is it possible to get the PLL to function from that pin?
Device is MAX10 10M16SAE144I7G
Please refer below link. Figure 7 indicates "Each clock source can come from any of the two or four clock pins located on the same side of the device as the PLL."
So, you cannot connect a GPIO pin to the PLL. GCLK networks are for the outputs of the PLL.