Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Running U-Boot SPL on custom hardware (Cyclone V)

New Contributor I

Hi. I have been following the SoCEDS and Arm Development Studio example for running a preloader on custom hardware. 

I successfully did this on the DE10-Nano using my own solution, linked here.

When I try to do the exact same on my custom PCB which uses the exact same SoC FPGA as on the DE10-Nano (5CSEBA6U23I7), I get the error shown in the screenshot. I changed the DDR3 SDRAM width and number of DQ groups in HPS system in Quartus accordingly.

Basically, my custom hardware doesn't like using the same make config as the DE10-Nano, even though they are the same SoC FPGA chip. Does anyone have any suggestions for generating a working preloader which can bring up SDRAM on custom hardware (not on a commercial development kit). 


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Yes, you need to manually change the device tree boards settings and configuration based on your Terasic device as the peripherals are different as compared to the Dev Kit's. If the custom hardware is however built based of the GHRD you can use the Dev Kit's device tree to compile as the peripherals are based of the Dev Kit's.


Regarding the DDR3, you may want to check if the calibration can pass when using on the FPGA (not HPS), to see if it would calibrate. If this passes, then you integrate to the HPS. Did you re-compile the everything, the preloader etc. after changing the DDR3 of HPS?

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