Hi all, this is my first time posting in AlteraForum so please be lenient if I am currently violating posting regulations. I will absorb all feedback since I plan to be back here often.
So my issue is I have a custom board with Stratix III and Micron LPDDR2. I am using the NIOS SOPC builder with DDR2 High Performance II Controller.
Everything compiled okay and I am now trying to assign pins to get through the Fitter tool.
It seems that Quartus would not allow the mem_clk and mem_clk_n to be assigned to PLL pins. I have made the research and found that it is pretty much a golden rule not to assign these signals to PLL.
However, I have first developed the same simple IP on the
cyclone iii started kit from Altera but their example nios code with ddr
assigns the clk and clk_n pins to plL.
Does that mean that there is a workaround setting to allow this that the examples of Cyclone III Starter Kit has enabled in their project?
If not, is it possible that this rule does not apply to the Cyclone III but applies to the Stratix III?
