Driving DCLK pin after FPGA configuration

[Altera_Forum]

Hi, 

 We are using 10CL016 FPGA and configuring it in Passive serial mode from a Host processor. The SPI clock is connected to the DCLK pin of FPGA.  We need to use the Host SPI interface even after configuration is done. We see that as per datasheet DCLK pin can't be used as I/O after configuration in passive serial mode. Hence, we have connected the same clock to one more adjacent I/O pin. This will enable us to use the SPI interface after configuration through this I/O, however after configuration DCLK pin will also be driven at the same time.  Is it fine to drive the DCLK pin even after configuration is over? Will it create any issues?  Regards Raja

[Altera_Forum]

Yes - you can continue to drive DCLK. 

 Cheers, Alex

[Altera_Forum]

Hello Alex, 

 Could you please confirm that "drive" specifically includes the concepts "clock" and "toggle", and that you not only mean "drive statically (EITHER continuously '0' OR continuously '1')"?

[Altera_Forum]

Yes - you can toggle DCLK continuously, it need not be static - although this is better from a power dissipation perspective. 

 Cheers, Alex

[Altera_Forum]

OK, thank you!