Driving differential clock from Cyclone III Dev Board to daugther card

[Altera_Forum]

Hello, 

 I am attempting to drive a differential clock out of the Cyclone III Development Board (EP3C120F780) to the "Data Conversion HSMC" daughter card. I want to clock data to a 14-bit DAC on the daughter card. I am using the HSMC "B" connector (the "A" connector has another card on it).   I am using the ALT_OUTBUF_DIFF primitive to drive a differential LVDS clock from PLL0 on the FPGA to a differential-to-LVDS clock multiplexer (ICS854054) on the daughter card.     When I assign all of the data and clock pins on the FPGA to their corresdponding pins on the HSMC connector, I receive the following error:   Error: Pad 283 of non-differential I/O pin 'DAC[0]' in pin location AE28 is too close to pad 286 of differential I/O pin 'HSMB_CLK_OUT_P1' in pin location AD27 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.   Obviously, the data lines and clock are hard wired through the daughter card, the HSMC connecter to the FPGA and I do not see a way the move the data lines away from the clock.   Am I doing this correctly? What is the best practice to output a clock from the Cyclone III to a daugther card?   Any help appreciated!

[Altera_Forum]

I don't exactly understand the problem. There should be no distance required between single ended and differential outputs. Distance rules only apply to differential inputs or bidirectional I/Os in relation to single ended outputs. 

 To implement a differential output, you don't need an ALT_OUT_BUF primitive, just assign the respective differential IO standard to the noninverted output of a differential pair.

[Altera_Forum]

@FvM, thanks for the reply. Are you saying that this particular distence rule is improper? In that case, how do I removed it? 

 Also, I am using ALT_OUTBUF_DIFF to convert from single ended clock from the PLL to differentia outputl. Is there another way to do this? Just using a NOT gate to generate one side of the differential will cause clock skew, would it not?

[Altera_Forum]

if you assign the single ended signal to be an LVDS output it should automatically assign the negative output

[Altera_Forum]

I tried removing the ALT_OUTBUF_DIFF so as to let the compiler assign the negative output. But this does not solve the problem. I still get the follow error: 

 Error: Pad 284 of non-differential I/O pin 'DAC[1]' in pin location AE27 is too close to pad 282 of differential I/O pin 'DAC_CLK_OUT_P' in pin location AC26 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.

[Altera_Forum]

I just put in a service request and I'm waiting to hear from them.