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Dual Modulus Divider

Altera_Forum
Honored Contributor II
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Hola All, 

 

this is my first attempt at a dual modulus divider. Eventually I want to use it in a Fractional_N PLL, but one step at a time. I still have to see how it holds up in a gate-level simulation. You can see part of the functional simulation below. the output follows the input when the division is set to 1 or 0. Around the 480 mark you see the pulses on Y being half that of clk, which makes sense because the division is 2 ( Num + 1), because Np1 is high. 

 

Anyway, I'm still quite the newb so if you have any suggestions let me know. 

 

 

http://sphotos.ak.fbcdn.net/hphotos-ak-ash2/hs014.ash2/34080_10150216062425055_754135054_13088368_6268216_n.jpg  

 

 

Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; ---------------------------------------> Entity Mod_Div_1 is Generic(k : integer :=3); Port( clk : in std_logic; Num : in Unsigned (k downto 0); Np1 : in std_logic; Y : out std_logic ); End Mod_Div_1; -----------------------------------------> Architecture Int_N of Mod_Div_1 is Signal Count :integer Range 0 to ((2**(k+1))-1); Signal Y_int2 : std_logic :='0'; Begin Y <= clk when (((Num = "00" or Num = "01") and Np1 = '0') or (Num = "00" and Np1 ='1')) else Y_int2; ---------------- Divider code ------------------------------------- N_Divide : Process(clk) Variable count_int : integer range 0 to ((2**(k+1))-1) :=0; Variable Num_Val : Integer range 0 to ((2**(k+1))-1); Variable Y_int : std_logic :='0'; Begin Num_Val := TO_INTEGER(Num); if (Np1 = '1') then Num_Val := Num_Val + 1; End if; if(clk'EVENT and clk ='1' and (Num_Val /= 0 or Num_Val /= 1)) then count_int := count_int + 1; if(count_int = Num_Val) then Y_int := '1'; count_int :=0; Else Y_int := '0'; End if; if(count_int > Num) then count_int := 0; end if; Y_int2 <= Y_int; End if; Count <= count_int; End Process N_Divide; -------------------------------------------------------------------- End Int_N;
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