Dynamic Phase Shift Q13.1

[Altera_Forum]

I am currently using a Cyclone V device and was able to successfully dynamically change the frequency back and forth using the PLL Reconfiguration megafunction.  

 I am not getting correct results when writing to the phase register. When writing a negative phase shift, the output shifts twice as much as it should. When doing a positive shift, the output does not shift at all.  Here is what I am doing and results I've seen:  Using the sources and probes feature over the JTAG, I setup an interface into the state machine and other blocks (PLL, PLL Reconfiguration): https://www.alteraforum.com/forum/attachment.php?attachmentid=8106  https://www.alteraforum.com/forum/attachment.php?attachmentid=8107  https://www.alteraforum.com/forum/attachment.php?attachmentid=8108   pll is setup as follows: https://www.alteraforum.com/forum/attachment.php?attachmentid=8109   https://www.alteraforum.com/forum/attachment.php?attachmentid=8111  advanced parameters copy and pasted here:   m-counter hi divide 4   m-counter low divide 4   n-counter hi divide 1   n-counter low divide 1   m-counter bypass enable FALSE   n-counter bypass enable FALSE   m-counter odd divide enable FALSE   n-counter odd divide enable FALSE   c-counter-0 hi divide 20   c-counter-0 low divide 20   c-counter-0 coarse phase shift 11   c-counter-0 vco phase tap 0   c-counter-0 input source ph_mux_clk   c-counter-0 bypass enable FALSE   c-counter-0 odd divide enable FALSE   c-counter-1 hi divide 2   c-counter-1 low divide 2   c-counter-1 coarse phase shift 1   c-counter-1 vco phase tap 0   c-counter-1 input source ph_mux_clk   c-counter-1 bypass enable FALSE   c-counter-1 odd divide enable FALSE   c-counter-2 hi divide 20   c-counter-2 low divide 20   c-counter-2 coarse phase shift 6   c-counter-2 vco phase tap 0   c-counter-2 input source ph_mux_clk   c-counter-2 bypass enable FALSE   c-counter-2 odd divide enable FALSE   vco post divide counter enable 2   charge pump current (ua) 20   loop filter bandwidth resistor (ohms)  4000   pll output vco frequency 400.0 MHz   k-fractional division value (dsm) 1   feedback clock type gclk   feedback clock mux 1 glb   feedback clock mux 2 fb_1   m counter source mux ph_mux_clk    I have modified the state machine from AN661 so that I may choose to reconfigure the PLL to two different frequencies or phase shift by two different amounts (in either direction). Using the following procedure I could successfully change the frequency dynamically: 

1. Power unit on. 
2. Choose “data_sel” (0 = 75MHz, 1=100MHz) 
3. Choose “freq_or_phase” as ‘0’ (0=frequency, 1=phase) 
4. Bring “start” low if it isn’t already 
5. “Down_up” is a don’t care for changing the frequency 
6. Raise “reset” and then bring back low (gets everything in a known good state. PLL will start out as follows 10MHz: 

  a. C0 = 10MHz, phase shift = 25000 ps  b. C1 = 100MHz, phase shift = 0 (used as the system clock for other logic/state machine)  c. C2 = 10MHz, phase shift = 45 degrees  7. To start a frequency reconfiguration, raise the start signal high which will initiate the state table to reconfigure the PLL. This can be successfully done back and forth between the 75MHz and the 100MHz.   to be continued in next post (hit picture limit)

[Altera_Forum]

Here is a signal tap screenshot of the state table writing to the PLL reconfiguration block: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8112   now to change the phase of c0 only. 1. Power unit on 2. Choose “data_sel” as ‘1’ (0=0x50 counts, 1=0x18 counts) 3. Choose “freq_or_phase” as ‘1’ (0=frequency, 1=phase) 4. Bring “start” low if it isn’t already 5. Bring “Down_up” low if it isn’t already. (0=Negative shift, 1=Positive shift) 6. Raise “reset” and then bring back low (gets everything in a known good state. PLL will start out as follows 10MHz:  a. C0 = 10MHz, phase shift = 25000 ps  b. C1 = 100MHz, phase shift = 0 (used as the system clock)  c. C2 = 10MHz, phase shift = 45 degrees 7. To start a dynamic phase shift, raise the start signal high which will initiate the state table to reconfigure the PLL. A Negative phase shift can be repeatedly sent to keep shifting the output, but the phase shift is double what is expected! A positive phase shift, however, does nothing.   results writing a negative phase count of 0x50 to c0 - VCO running at 400MHz - Phase Shift Resolution = (1/400MHz)/8 = 312.5pS - Phase shift of 0x50 = 80 counts -> 80 x (312.5pS) = 25nS actual phase shift seen at output (on scope) = 50ns instead of 25ns (direction bit set to ‘0’) https://www.alteraforum.com/forum/attachment.php?attachmentid=8113  writing a positive phase count of 0x50 to c0 - VCO running at 400MHz - Phase Shift Resolution = (1/400MHz)/8 = 312.5pS - Phase shift of 0x50 = 80 counts -> 80 x (312.5pS) = 25nS actual phase shift seen at output (on scope) = 0 ns (does not move – direction bit set to ‘1’) https://www.alteraforum.com/forum/attachment.php?attachmentid=8114   Has anyone seen anything similar? I am currently using a Cyclone V FPGA and running Quartus 13.1.  Any suggestions are appreciated!  Thank you

[Altera_Forum]

As a follow up for informational purposes, Altera has released an errata document that shows the phase shifting would not work in some silicon revisions of the Cyclone V FPGAs.  

 The document (at the time) is located here: http://www.altera.com/literature/es/es_cyclone_v.pdf ES-1035-2.1 last dated December 2013  Since then I have received a new version of the silicon that should have the dynamic phase shifting working, but it is still not working. My service request is still open (started in November of 2013) and there has been no conclusion yet.

[Altera_Forum]

If you are interested that others are looking into the problem, you should post a test design demonstrating the problem as Quartus archive.

[Altera_Forum]

Good point, I should have done this a while ago. I've attached my latest test project that uses a cascaded PLL as a .zip file. Just needs to be recompiled. 

 There is a signal tap enabled to see the signals while writing and In system memory constants that can be used to change the parameters before re-configuring the PLL.  There is also an Sources and Probes editor for triggering a Frequency reconfig, phase reconfig and to also provide a reset  On power up: The first PLL will output 125MHz, and I divided it by 4 using a counter and outputted the 31.25MHz signal to a test point The second PLL will output 31.25MHz and is also brought to a via When trying to do a positive phase shift (up_dn bit ='1') as it's setup, there output of the PLL does not move with respect to the divided down 125MHz clock. When changing the Phase constant to do a negative phase shift (up_dn bit ='0'), the PLL output will change by 2 times the amount than it should.  If the frequency reconfiguration is triggered, the second PLL output will reconfigure to 40MHz. The values may be changed to output any other desired frequency within the fractional PLL specifications.