Dynamic clock selection in Cyclone 4E

[Altera_Forum]

Does anybody know if it is possible to dynamically switch between 4 clocks of 1 PLL in a Cyclone IV E device? 

I tried several options, cascading clock control blocks, used 2 PLLs, each generating 2 of the 4 clocks, but I can't get it working. It looks like the clock control blocks are the limitation. Whatever I do, I'm getting errors on these blocks (ALTCLKCTRL).  There are so many resources on this device. This should be possible.  Any ideas?  Kind regards.

[Altera_Forum]

There are plenty of resources on the device and an intended way to use them. Assuming you're trying to drive a block of logic with one of four clocks, then you're trying something that, I'm pretty sure, isn't an intended mode of operating. 

 The only way I can see this working is if you have an external loop, something I frequently design into hardware. You can select one of your four clocks, drive it off the device and back into a dedicated clock pin which is used to drive your logic. That way you can chose which clock to use.  This method will result in greater jitter and an unpredictable delay to the resulting chosen clock. Depending on your application, neither of these may be of concern. Your choice if that is something you can live with.  Regards, Alex

[Altera_Forum]

--- Quote Start ---  The only way I can see this working is if you have an external loop, something I frequently design into hardware. You can select one of your four clocks, drive it off the device and back into a dedicated clock pin which is used to drive your logic. That way you can chose which clock to use.  This method will result in greater jitter and an unpredictable delay to the resulting chosen clock. Depending on your application, neither of these may be of concern. Your choice if that is something you can live with.   --- Quote End ---     Hi Alex,  Thanks for your respons.  I designed my board so that all my spare clock input lines are connected to spare outputs. Till now I used these as external loops.  But like you mentioned, this results in greater jitter, which is undesirable in my design. I can live with the unpredicable delay.  Kind regards

[Altera_Forum]

As you found out, you're not going to be able to get there with the clock control blocks ("They don't work that way.") 

 In one of my systems, I was able to use the HDL clock mux from the Altera cookbook successfully.  There is also this relevant thread topic: http://www.alteraforum.com/forum/showthread.php?t=2388   Good luck.

[Altera_Forum]

In my reading of the Cyclone IV device handbook, dynamic clock selection is possible between two PLL outputs, not four. But I never used it myself.  

 Might it be possible to achieve the intended clock switching with PLL reconfiguration?

[Altera_Forum]

Well, that's a lot of reading for me the coming days. 

I will do some experiments and post the results. Please be patient, because it's a side-project. I can only spend limited time on it.  Thanks for your replies. They're very useful.