Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Dynamic reconfiguration and dynamic phase shifting

Altera_Forum
Honored Contributor II
1,194 Views

I have successfully implemented dynamic phase shifting in a Cyclone iv by putting in my own controller. Now I need to be able to dynamically reconfigure the same pll Frequency's. This is because the incoming clock is driven by different modules in different products so the incoming clock can change frequency. I'd like to be able to have an internal ram that can be written with by software to scan into the Cyclone iv scan port. Has any one done this? I've been looking at the examples and megafunction users guide and its just confusing. So what I need to do is reconfigure the frequencies of the pll after power up with software. Then that will not change again. After that I change the phase of the clocks on demand as part of normal operation. One method is pushing one parameter into the scan chain but I would have to do this 4 times one for each clock. The other method is by .mif file but this incoming clock has multiple possible values. The other confusing part is the scan clock must remain the same so if I used altpll_reconfig then I need to understand how to merge that in with dynamic phase shift controller. 

 

Thanks, 

 

Elaine
0 Kudos
0 Replies
Reply