I would like to dynamically reconfigure my Arria 10 Transceiver PHY. I use reset controller IP and reconfiguration interface for the purpose. From the user guide, I understand that the steps to perform dynamic reconfiguration are as follows.
Step 1: Apply tx_analogreset, pll_powerdown, tx_digitalreset, rx_analogreset and rx_digitalreset while pll_cal_busy, tx_cal_busy and rx_cal_busy is low.
Step 2: Perform dynamic reconfiguration by setting registers to corresponding values.
Step 3: Deassert reset
When I use the default model for reset controller, the assertion and deassertion of resets are done according to the time duration we specified. How can I ensure that enough time is available for dynamic reconfiguration before resets are deasserted?? Is there any signal that inform the reset controller that dynamic reconfiguration is complete and the reset controller can release resets?
The question arises because the reset assertion and deassertion are controlled by reset controller whereas reconfiguration is controlled by Avalon master!!
