EMIF example design calibration fail on Stratix10

[Altera_Forum]

Hi guys, 

 I'm testing EMIF on Statix 10 DevKit with RLDRAM3 and I'm running into some issues that have been blocking me for more then a week. Here is what I did: I chose a preset "RLDRAM3 MT44K16M36-093E" based on this documentation (related to Arria10) : https://www.altera.com/documentation/iga1434736665480.html#iga1439506702904 Then I generated the example design. After programming the S10 dev kit FPGA, I got the following signals status from the ISSP gui :  emif_s10_0_status_local_cal_fail = 1 emif_s10_0_status_local_cal_success =0 emif_s10_0_tg_0_traffic_gen_fail = 1 emif_s10_0_tg_0_traffic_gen_pass = 0 emif_s10_0_tg_0_traffic_gen_timeout = 1  From what I understood the design didn't even pass the calibration phase.  I have been reading many documents about S10 EMIF, however none of them helped me to get over this issue. How can I be sure that I'm using the correct preset. any document on that would be a great help?   which parameters could cause this problem ? where can i find the presets of the HILO memory Daughtercards ? I have to mention that I left the pin assignment for quartus to handle. Fitter auto pin assignment is aligned with the pin assignment of the EMIF example that came within the S10 dev kit package.

[Altera_Forum]

Dev kits come with complete example designs. You should use that instead of what you generate from the parameter editor. However, on the Example Designs tab of the EMIF parameter editor, is your board listed? Make sure you select your board before generating the example design. 

 If your board is not listed, use the examples that came with the kit.

[Altera_Forum]

I will try the example designs that came in the dev kit 

By the way my dev kit is not listed  Is there any way I can add it ??