EP2C8Q208C8N can use PCle's high-speed serial transceiver

[EE通行]

We want to design a high-capacity data acquisition device (32-bit 128G), and the FPGA chip used is EP2C8Q208C8N. Due to the fact that EP2C8Q208C8N only reserves 2 external DDR4 I/O ports, it is difficult to meet our design requirements with only two memory. Therefore, we want to use the PCle interface of EP2C8Q208C8N in conjunction with a high-speed serial transceiver to connect a large capacity memory module externally for implementation. However, we are not familiar with the PCle interface of EP2C8Q208C8N. Can you provide us with some case studies and materials for reference and learning. Meanwhile, we have not found any high-speed serial transceivers that are compatible with EP2C8Q208C8N. Can you recommend some to us. In addition, are there any issues with our design when using EP2C8Q208C8N, and can it theoretically meet our design requirements?

[Wincent_Altera · Accepted solution]

Hi,

For Cyclone II PCI Express, you may refer to our device handbook

Cyclone® II Device Handbook

The recomendation for customers is to use PCIe Hard IP, as users no need to do intergration with 3rd party PHY chip.

There are many PCIe reference designs available in application note AN456.

Page 12 of Application Note AN456 has the link to download the PCIe example designs for different dev kits. You may select Arria II

Regards,

Wincent_Intel

[Wincent_Altera]

https://cdrdv2-public.intel.com/666650/an456-683541-666650.pdf

[EE通行]

Dear wchiah,

I am very sorry for not being able to review and respond to your response in a timely manner as I have been busy designing circuits recently. Thank you very much for your help.

Best wish，

EE通行

[wuyuetian]

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[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[Wincent_Altera]

Hi 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.  

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause 

Hence, This thread will be transitioned to community support.  

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Wincent_Intel 

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey. 

[FvM]

Hi,
several wrong respectivly misleading answers above..

Cyclone II has no PCIe interface at all. The first Cyclone chip with PCIe interface (and hard IP) is Cyclone V GX.

Arria II is the first FPGA series providing PCIe hard IP.

[EE通行]

Hi,

Regarding your point that "Cyclone II doesn't have a PCIe interface at all. The first Cyclone chip to have a PCIe interface (and hard IP) was Cyclone V GX," we noticed while researching. At the same time, the data explains that Cyclone II requires PCIe interfaces to be simulated through FPGA I/O pins for external circuit design or the use of bridge chips. Is there a PCle protocol within it? Can PCle2.0 be used?