EP3C LVDS : external PLL

[Altera_Forum]

Hello everyone, 

I have specific question on configuring CycloneIII LVDS with external PLL. I’ve searched thru the forum but did not find info relevant to my case    I need to run two similar LVDS Tx links from the single PLL. Speed – 210Mbps, serialization factor 8, Tx width is 16 channels  Per my understanding I nend to configure PLL with two outputs -#1 105 MHz(the base rate / 2 ) with minus 90 degrees phase shift,# 2 26.25 MHz (base rate / serialization factor = 210/8 ) with minus 22.5 degrees ( that is 180 degrees / serialization factor)    The PLL output# 1 is called fast clock,# 2 is called slow clock. Both fast and slow clocks are supplied to ALTLVDS IP generated by MegaWizard. Also ALTLVDS input data is reclocked on slow clock. The slow clock is also used as a LVDS source clock – the clock is transmitted by the FPAG together with Tx data    So far I was just following application note AN479. Unfortunately LVDS data on the is received as garbage. If I use dedicated PLL to each LVDS Tx link – that is letting MegaWizard instantiate PLL for ALTLVDS IP – then LVDS data is looking fine.    I suspect I’m missing something on External PLL configuration (need to use separate clock as LVDS source clock). I would greatly appreciate any hints on properly configuring External PLL and connecting External PLL to ALTLVDS and I/O

[Altera_Forum]

Alright, converting dialog to monologue - answering my own question :) 

 In order to share one PLL between two different TX LVDS blocks you need to apply the same approach as with sharing one PLL between Rx and Tx blocks - connect lvds_0_tx_inst.pll_areset and lvds_1_tx_inst.pll_areset ports to the same reset signal; connect lvds_0_tx_inst.tx_inclock and lvds_1_tx_inst.tx_inclock ports to the same clock source.   In this case the fitter will merge two LVDS TX Plls into one pll, look for "Info: Successfully merged PLL <pll_0> and PLL <pll_1>" message in the processing log