Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 讨论

EP4CE15M9I7N configuration

XQSHEN
新手
1,189 次查看

 

Hello,

 

Any issue with below configuration?

As status, conf_done, MSEL, JTAG are using different pull up supply voltage, I am not sure if there is any issue.

XShen1_0-1638687648608.png

 

0 项奖励
6 回复数
NurAiman_M_Intel
1,170 次查看

Hi,


Thank you for contacting Intel community.


Please refer to Cyclone IV pin connection guidelines. You can get the Cyclone IV handbook from the link below, and download the pin connection guidelines from the handbook.


https://www.intel.com/content/www/us/en/products/details/fpga/cyclone/iv/docs.html?s=Newest


Regards,

Aiman


0 项奖励
XQSHEN
新手
1,156 次查看

I think I followed the guide.

As status, conf_done, MSEL, JTAG are using different pull up supply voltage, do you see any issue?

0 项奖励
NurAiman_M_Intel
1,146 次查看

Hi,


It is advisable to follow pin connection guidelines as the guideline was tested and approve by Intel.


Regards,

Aiman


0 项奖励
XQSHEN
新手
1,126 次查看

I appreciate if you can direct answer my question .

0 项奖励
NurAiman_M_Intel
1,104 次查看

Hi,


We do not know the potential risk, apart from our connection guidelines as we have not tested it.


Apologize for the inconveniences.


Regards,

Aiman


0 项奖励
NurAiman_M_Intel
1,062 次查看

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


0 项奖励
回复