Hi can someone help me with reading data from RAM, pleasemy code is very easy look:
module dds_generator(clk,signal_output); input wire clk; output wire signal_output; reg phase_acumulator; initial phase_acumulator = 32'd0; //assign signal_output = phase_acumulator; ram1_port sin( .address(phase_acumulator), .data(), .outclock(clk), .we(1'b0), .q(signal_output)); always@( posedge clk ) begin phase_acumulator <= phase_acumulator + 32'd85899; // end endmodulecompile project without errors but not use any CPLD resources :confused: http://www.alteraforum.com/forum/attachment.php?attachmentid=12567&stc=1 RTL viewer : I thinks this is good http://www.alteraforum.com/forum/attachment.php?attachmentid=12568&stc=1 I dont know why :( thaks for help me
Is your signal_output signal connected to pins outside of the FPGA? If not the whole module will be optimized away by the synthesizer.How do you load data in the RAM? I don't know if the synthesizer is smart enough, but it's possible that if it detects that you can never write anything in the module and that it's just initialized with zeros, that it will "optimize" your code by just outputting zeroes.