Does nCE=High only disable the Configuration pins or would other pins also be affected? And does "disable" imply that the affected pins are high impedance?What happens if nCE is driven high in User Mode after Configuration? Would the part continue to operate internally and on any unaffected pins?
Hi,--- Quote Start --- Does nCE=High only disable the Configuration pins or would other pins also be affected? --- Quote End --- No, FPGA will remain configured and works fine if nCE high during user mode. --- Quote Start --- What happens if nCE is driven high in User Mode after Configuration? Would the part continue to operate internally and on any unaffected pins? --- Quote End --- Intel FPGA will not lose its configuration contents if the nCE pin is pulled high during user mode https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01102011_672.html Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Hello Anand,Thank you for the reply. Could you elaborate on the effect of nCE=High in User Mode, please? Which pins can nCE affect? Why is it recommended that nCE be held low during User Mode, for example also in the link you provide?
Hi,The nCE is active low chip enable which enables FPGA. The nCE needs to be low all the time from power up until under mode. It is not that recommended for the nCE cannot be high in user mode. If the nCE is high (regardless during configuration or user mode), the FPGA will not be able to function correctly. For example, if nCE high the JTAG will not work. Most likely the design and IO pins will not work correctly even though the FPGA has been configured. You can check any FPGA pin connection guideline mentioned: When the nCE pin is low, the device is enabled. When the nCE pin is high, the device is disabled. https://www.altera.com/documentation/lit-dpcg.html When the nCE is high causing to disable the device, there is no reason for pulling the nCE high at any time. There is no timing since the nCE should be low all the time. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
nCE has a purpose in two situations- multiple FPGAs configured from a single memory - enabling access to the AS or AP configuration memory for an external host If non of these conditions apply, nCE would be permanently tied to GND.
Hello FvM,Thank you for the reply. The original intention of this thread was to clarify the effect of nCE=High during i) Configuration and ii) User Mode. Do any pins become high-Z if not already so? If so, which pins? Any other effects on pin functions, impedance and internal configuration? We have had (only) two observations up to now: 1) Intel FPGA will not lose its configuration contents if nCE is pulled high during User Mode, and 2) The JTAG will not work during both Configuration and User Modes if nCE is pulled high. It seems that - more than this - no-one really knows more precisely what the effect of pulling nCE high might be. We wanted to understand the effect of nCE=high because we had the following design concept: 1) use FPP to configure the FPGA via a Host processor's parallel bus 2) reuse this parallel bus during User Mode for Host to FPGA communication 3) however, this parallel bus is also shared with a Flash device to allow the Host to initially boot So we were investigating the possible use of nCE to ensure that the FPP pins are inactive and not clocking any internal configuration function during 2) and 3) and on occasion when the Host's boot flash mentioned in 3) should be updated. The Note under C10GX51003 2017.11.10 says in respect of AS configuration pins: "If you wish to gain control of the EPCQ-L pins, hold the nCONFIG pin low and pull the nCE pin high. This causes the device to reset and tri-state the AS configuration pins." It would be great to have confirmation of this for the FPP-related pins too, since they differ from the AS pins. This would confirm the feasibility of 3) above. We could hold nCE high in this case. And for 2) above, it would be great to see that, for example, if nCE is pulled high, only Configuration (and JTAG) functions are made inactive but that User Mode pin functions (including those shared on the Configuration pins) continue to be unaffected. It seems logical to expect that Configuration pins should become inactive upon entering User Mode and that they may therefore be toggled at will with no undue User Mode effect, which would greatly obviate the need for the nCE considerations above. Yes, buffers would be a way of decoupling the affected dedicated configuration pins, but it would be great to KNOW that a buffer is definitely necessary of that it definitely is not necessary in order to prevent unexpected User Mode behaviour. Or that nCE may else be useful in some way.
Yes, taking nCE high tristates all configuration pins on the FPGA side, so that you can e.g. reprogram the AS memory. The pins are not generally tristated in user mode, the altasmi IP is even clocking DCLK permanently.There's no need for buffers between AS memory and FPGA, just control nCE respectively.