Upon starting up the 10M02SCU169 I see a spike at pins assigned as outputs that trying to drive low after configuration. I measured the pins of 1.8V and 3.3V bank and still see a spike on any pin assigned as output and to be pulled low. The spike sometimes exceed the VCCIO bank then the signals will go low. For example if the signal is in a 3.3V the spike will go as high as 4.3V before the signal is driven low. I used the DEV-OE reset pin and pulled it low, so that all outputs are in tristate. Even then I still see a spike at the pins configured for outputs. Does anyone have any ideas on how I can fix this? My MAX10 is powered by 3.3V, I measured spikes at output pins on both 1.8V and 3.3V io banks. Thanks in advance for your help.
Hi,You need to check the ground, It may be one of the issues. 1. Is measuring instruments (oscilloscope) connected to common ground while measuring. 2. Are you using development Kit? Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Thanks for the reply Anand. I am using the CPLD on our custom designed PCB board. The oscilloscope is using the same ground as the power supply. I just checked and noticed that the spike happens before nSTATUS goes high. So it seems like it happening during the power up state and reset state before the configuration state. All output pins should be in tristate at this time according to the state machine in the Configuring Altera FPGAs pdf.
Not sure if your voltage measurements are reliable, but seeing outputs pulled high by a weak pullup during power-on is normal operation of all Altera FPGA. Outputs required to keep low level during power-on must be equipped with a strong pull-down resistor, e.g. 500 ohms to 1k.Better use active low signaling for critical signals.