Efficient Signed Multiplier with good timing

[HZoha]

I am making a signed multiplier for that i have created half adder, full adder, ripple carry adder and then finally a multiplier. The code is shown below. How can i make it faster to achieve better timing. My final task is to make a fir filter operating running at 100Mhz. This filter use multiple multiplication operation(by using my multiplier). So Can you help me to make my design better by some optimizing technique like pipelining or parallelism or other??

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[CheePin_C_Intel]

Hi,

As I understand it, your final goal is to create a FIR filter operating at 100MHz. For your information, we have had FIR II IP available which could help to implement FIR filter operation. Just wonder if you have had a chance to take a look into our FIR II IP to see if it can meet your target requirement?​

[CheePin_C_Intel]

​You may refer to the following FIR II user guide for further details, thank you.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fir_compiler_ii.pdf