Emulated LVDS

[Altera_Forum]

hello everybody :) 

i'm using Stratix III. what is the diffrence between the dedicated LVDS IO to the emulated LVDS IO?    thanks;)

[Altera_Forum]

Emulated LVDS is actually voltage mode: Signal is sent to the positive pin, same signal go through one not gate inside FPGA and be sent to the negative pin. 

Dedicated LVDS IO buffer is current mode.

[Altera_Forum]

As a practical difference, the achievable data rate is considerably lower.

[Altera_Forum]

can I reach 500Mhz with the emulated output LVDS channles?

[Altera_Forum]

In the Stratix III Device Handbook, you find table 1–24. high speed i/o specifications 

 It tells, maximum LVDS data rate is 550 MHz with LVDS_E_3R IO-standard and C2 speed grade.

[Altera_Forum]

And which maximum data rate can i achieve in cyclone III EP3C16Q240C8N ? In datasheet i found only for Cyclone III LS mini LVDS max.speed 311Mbps. It is same in Cyclone III ? 

Thank you.

[Altera_Forum]

Thanks for opening this thread, it answered my question. 

However, I have a quick follow-up question:  It says about emulated LVDS in the pin connection guidelines: "External resistor network is needed for emulated LVDS output buffers."  What is meant by that?  Thanks Adam

[Altera_Forum]

You want to read Cyclone III Device Handbook, Chapter 7. high-speed differential interfaces in the cyclone iii device family 

 See e.g. Figure 7–3. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks  For other devices than Cyclone III, do a manual text search for "emulated LVDS".