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module bcd_seven_seg(SW,HEX0,HEX1,Hex2,LEDG);
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2;
output [9:0] LEDG;
wire [6:0] hex0,hex1,hex2;
HEX0 = ~hex0;
HEX1 = ~hex1;
HEX2 = ~hex2;
bcd_seven_seg_behavioral u0(SW[3:0],HEX0);
bcd_seven_seg_behavioral u1(SW[7:4],HEX1);
bcd_seven_seg_behavioral u2(SW[9:8],HEX2);
endmodule
module bcd_seven_seg_behavioral(bcd,hex);
input [3:0] bcd;
output reg [6:0] hex;
always @ (bcd) begin
case(bcd)
4'b0000: hex <= 7'b0111111;
4'b0001: hex <= 7'b0000110;
4'b0010: hex <= 7'b1011011;
4'b0011: hex <= 7'b1001111;
4'b0100: hex <= 7'b1100110;
4'b0101: hex <= 7'b1101101;
4'b0110: hex <= 7'b1111101;
4'b0111: hex <= 7'b0000111;
4'b1000: hex <= 7'b1111111;
4'b1001: hex <= 7'b1100111;
4'b1010: hex <= 7'b1110111;
4'b1011: hex <= 7'b1111100;
4'b1100: hex <= 7'b0111001;
4'b1101: hex <= 7'b1011110;
4'b1110: hex <= 7'b1111001;
4'b1111: hex <= 7'b1110001;
endcase
end
endmodule
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1) Verilog is a case sensitive language. Check your first module header: Hex2 ==> HEX2
2) lines 6-8 need a type declaration, like (probably) 'wire'. Ie: wire HEX0 = ~hex0; etc
3) (minor) line 11 first arg is only 2 bits wide but function wants 4 bits. Change to: bcd_seven_seg_behavioral u2({2'b00,SW[9:8]},HEX2); to eliminate the warning.

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