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AM GETTING THIS ERROR WHILE ANALYSINING THE DESIGN
CAN SOMEONE SUGGEST WHAT COULD BE THE PROBLEM...
I have checked the qsys also the name are same and i have also exported the pin
THANKS AND REGARDS
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Hi,
Here are the possible solution for your issue:
- Check the Qsys system to ensure the missing port exists in the design
- If you have duplicates or more than one output folder, please remove the unused output folder, the error might be Qsys confused between the output folders.
Let me know if the problem persist.
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hi,
thanks for the reply...
as you said i checked the missing port but there is a port in the qsys....
i am attaching the project here... can you please check and let me knw...
the qsys design is in the RSU floder-> onchip.qsys
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Hi,
I will check the project.
Meanwhile can you discard any unused project/previous unused project in your folder, or simply create a clean one in a new folder, see if it works.
Here is a similar discussion regarding the error in case I am late with the update:
https://forums.intel.com/s/question/0D50P000046IjYRSA0/system-verilog-pass-typedef-struct-packed-between-modules-error-12002-port-x-does-not-exist-in-macrofunction-y
Regards.
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hi,
as per your suggestion i tried deleting all the unwanted folders and comiling it again but still the same problem persist.
can you let me know whatelse can be done
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Hi,
Are you using MAX10 board? Also, how did you do the design? Is it from a tutorial that you follow or any guides.
Regards.
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am using max10 board. the design is based on the some guidance.
But now am designing I2C communication for that am following the below manual.
https://sites.ualberta.ca/~delliott/ece492/appnotes/2014w/G5_I2C_Driver_Improved/G5%20-%20I2C%20Driver%20Appnote.pdf
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Hi,
Is the above manual also reporting the same error?
If you still facing the error can you do a clean build of the project and share it to me.
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