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Error (16021) using 10M08SCE144C8G

alex100
Beginner
1,794 Views

I'm utilizing the MAX10 FPGA, specifically the 10M08SCE144C8G model, to generate sweeping sinewave signals using lookup tables and multipliers. However, during compilation, I encountered the following error message:

"Error (16021): You specified a configuration mode that includes memory initialization, however memory initialization is not supported by the selected device. In the Device and Pin Options dialog box, choose a configuration mode without memory initialization."

I attempted to address this issue by making adjustments in Assignments -> Device and Pin Options -> Configuration mode. Unfortunately, choosing either of the options led to the same error. I'm seeking assistance to resolve this issue. Thank you in advance.

 

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16 Replies
FvM
Valued Contributor III
1,764 Views
Hi,
MAX10 SC type doesn't support memory initialization and can't implement lookup tables. Trying to implement it causes synthesis failure.
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FvM
Valued Contributor III
1,739 Views

Hi,
I checked which errors are raised in which situation.

You get error 16021 if you try to compile 10MxxSC with memory initialization configuration.
Compiling a design with initialized RAM but without respective configuration gives error 16031.

If you continuously get error 16021, you didn't manage to change the configuration. You can check project .qsf, it should e.g. contain an assignment
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"

Your problem might be caused by a strange behaviour of the Device and Pin Options dialog. The displayed Configuration Mode does not necessary reflect the actual setting because it only shows legal values for the selected device. You need to change it to a different option and back  to the intended setting to change the internal value. 

I stated above that SC type can't implement lookup tables. That's not fully correct, it can't implement lookup table defined as initialized block ram (altsyncram IP). It compiles however inferred ROM without problems, except for a possibly large lcell utilisation.

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alex100
Beginner
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Dear FvM,

I would like to express my gratitude for addressing my queries.

1) Compilation Results:

I performed compilations with both 10M16SCE and 10M08SCE devices, yielding notable differences in outcomes.

For the 10M16SCE144C8G device, the compilation using Single Uncompressed Image (256Kbits UFM) was successful, as evidenced by the following details:

"----

Flow Status Successful - Thu Jan 25 17:47:39 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M16SCE144C8G
Timing Models Final
Total logic elements 7,807 / 15,840 ( 49 % )
Total registers 1088
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 562,176 ( 0 % )
Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )
----"

 

However, reverting to the 10M08SCE144C8G device (with Single Uncompressed Image (256Kbits UFM)) resulted in a failure, requiring 11,504 logic elements, exceeding the device's capacity:

"------
Flow Status Flow Failed - Fri Jan 26 11:27:49 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 11,504 / 8,064 ( 143 % )
Total registers 1196
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 387,072 ( 0 % )
Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )
------"

Furthermore, attempting to compile with "Single Compressed Image (720Kbits UFM)" on the 10M08SCE144C8G device also failed, displaying Error 16021. The details are as follows:

"-----
Flow Status Flow Failed - Fri Jan 26 10:57:35 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 5,815 / 8,064 ( 72 % )
Total registers 1107
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 92,672 / 387,072 ( 24 % )
Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )
 
 
Error (16021): You specified a configuration mode that includes memory initialization, however memory initialization is not supported by the selected device. In the Device and Pin Options dialog box, choose a configuration mode without memory initialization.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Error (171000): Can't fit design in device
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 4961 megabytes
Error: Processing ended: Fri Jan 26 10:57:35 2024
Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:04
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 147 warnings
----"

 

2) .qsf File Modification:

As you pointed out, there is a line in the .qsf file that reads "set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE." What steps should I take about this line?

 

3) Workaround Implementation:

This link
https://www.intel.com/content/www/us/en/support/programmable/articles/000074796.html?erpm_id=6573007_ts1706295120833
suggested a workaround:

"-------
Resolution
Signal declaration for memory_type should be changed from

signal mem : memory_type :=(others => (others => '0'));

to

signal mem : memory_type;

This is to ensure that memory is not initialized and there is no compilation error in the Assembler stage.
------"

I'm using Verilog language and am not sure how to implement this workaround.

Once again, thank you for your assistance.

 

 

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alex100
Beginner
1,706 Views

Hi FvM,

I appreciate your prompt response to my inquiries.

As you pointed out, the .qsf file contains the line

"set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE". 

What steps should I take about this?

 

I came across a suggested workaround on this link:

It suggests a workaround:


"-----
Resolution
Signal declaration for memory_type should be changed from

signal mem : memory_type :=(others => (others => '0'));

to

signal mem : memory_type;

This is to ensure that memory is not initialized and there is no compilation error in the Assembler stage.
-----"

Since I am using Verilog, could you guide me on how to implement this workaround?

Thank you once again.

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FvM
Valued Contributor III
1,682 Views

Hi,
the correct configuration mode can be set in Device and Pin Options dialog. I just wanted to explain why this possibly failed. Editing .qsf or sending the quoted assignment in tcl console will work, too.

I don't understand the workaround. A lookup table needs initialized signals. The problem is that it can't be implemented in block ram for MAX10 SC. You can refer to Quartus Verilog design template for 1-port RAM or initialized RAM, Quartus is compiling it into logic cells if the device doesn't support initialized memory.

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NurAiman_M_Intel
Employee
1,613 Views

Hi,


The workaround are using VHDL. You can just convert it to verilog.


Regards,

Aiman


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alex100
Beginner
1,597 Views


Hi FvM and NurAiman_M_Intel,

I appreciate your answers. My Verilog design includes a lookup table with 4096 addresses, and I need to store numbers associated with each address. It appears that the lookup table is the root cause of the issue.

Two challenges have left me puzzled:

1. It appears that the 10M0xSCE chip lacks flash memory, making it unable to store numeric data like a Lookup Table (LUT) or vector initialization. However, I understand that its logic cells can be utilized as a form of memory. Could you confirm if my understanding is correct?

2. As I showed earlier I successfully compiled the design using the 10M16SCE144C8G chip, with the output indicating "Total logic elements 7,807 / 15,840 ( 49 % )". However, when attempting to compile the same design using the 10M08SCE144C8G chip, it indicates "Total logic elements 11,504 / 8,064 ( 143 % )". I'm curious as to why more logic elements are needed in the latter case and would appreciate any insights you may have.

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NurAiman_M_Intel
Employee
1,496 Views

Hi,


To answer your question;


  1. If it is for core logic cell, your understanding is not correct.
  2. Please provide compilation report for this so we are able to analyze this further.


Regards,

Aiman


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Farabi
Employee
1,404 Views

Hi Alex, Do you have updates from previous request?


regards,

Farabi


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alex100
Beginner
1,361 Views
Using 10M016SCE144C8G and Single Uncompressed Image (256Kbits UFM) was successful. Need 7807 logic elements.
Using 10M08SCE144C8G and Single Uncompressed Image (256Kbits UFM) was unsuccessful. Need 11,504 logic elements.
 
This is the flow Summary (using 10M08SCE144C8G) after compiling:
 
 
"-----------------------------------
Flow Status Flow Failed - Thu Feb 15 11:01:02 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 11,504 / 8,064 ( 143 % )
Total registers 1196
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 387,072 ( 0 % )
Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )
Total PLLs 0 / 1 ( 0 % )
UFM blocks 0 / 1 ( 0 % )
ADC blocks 0
-------------------------------------"
 
 
The report during compilation is attached.
 
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NurAiman_M_Intel
Employee
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Hi,


  1. What is the setting when compiling those 2 devices? Is there any differences? (Compilation setting)
  2. Please also share the compilation report for 10M016SCE144C8G.
  3. Can you share your design in .qar?


Regards,

Aiman


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alex100
Beginner
1,236 Views


Hi NurAiman, 

1. I'm a bit uncertain about what you're referring to with '(Compilation Setting)'. The only alteration I made was within the 'Device and Pin Option' where I set the Configuration to 'Single Uncompressed Image (256Kbits UFM)' for both chips.

2. This is the flow Summary (using 10M16SCE144C8G) after compiling:


"-----------------------------------
Flow Status Successful - Wed Feb 21 09:48:40 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M16SCE144C8G
Timing Models Final
Total logic elements 7,786 / 15,840 ( 49 % )
Total registers 1088
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 562,176 ( 0 % )
Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )
Total PLLs 0 / 1 ( 0 % )
UFM blocks 0 / 1 ( 0 % )
ADC blocks 0

-----------------------------------"

3. I'm unsure about creating a .qar file. Could you guide me through the steps to make one?

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NurAiman_M_Intel
Employee
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Hi,


.qar file is basically an archived file. You may refer below for the steps;


https://www.intel.com/content/www/us/en/docs/programmable/683463/21-3/archiving-projects-for-service-requests.html


Regards,

Aiman


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NurAiman_M_Intel
Employee
1,084 Views

Hi,


Per our observation based on the compilation report, the error occur when using 10M08SCE144C8G is because the device does not support your design.


As you can see from the compilation report, the design has used all the Embedded Multiplier 9-bit elements 48 / 48 ( 100 % ), which is not enough for 10M08SC as the design need more hence it overused the Total logic elements 11,504 / 8,064 ( 143 % ) - , thus compilation is failed.




Family MAX 10

Device 10M08SCE144C8G

Timing Models Final

Total logic elements 11,504 / 8,064 ( 143 % )

Total registers 1196

Total pins 32 / 101 ( 32 % )

Total virtual pins 0

Total memory bits 0 / 387,072 ( 0 % )

Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )

Total PLLs 0 / 1 ( 0 % )

UFM blocks 0 / 1 ( 0 % )

ADC blocks 0


Your design need to use bigger device which is 10M16SCE144C8G that is suitable with your design.


Family MAX 10

Device 10M16SCE144C8G

Timing Models Final

Total logic elements 7,786 / 15,840 ( 49 % )

Total registers 1088

Total pins 32 / 101 ( 32 % )

Total virtual pins 0

Total memory bits 0 / 562,176 ( 0 % )

Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )

Total PLLs 0 / 1 ( 0 % )

UFM blocks 0 / 1 ( 0 % )

ADC blocks 0


Regards,

Aiman


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alex100
Beginner
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Appreciate all the replies. I believe I've found the answer.

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NurAiman_M_Intel
Employee
1,029 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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