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Error (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank

cdsteinkuehler
Beginner
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I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks).  The design was originally implemented using Quartus 15.0 however I have recently been attempting to update to newer versions of Quartus and have encountered some issues.

When compiled with Quartus 15.0, I have intermittent data integrity issues with the various DCFIFOs used in the design to bridge streaming video signals across different clock domains due to the embedded "set_false_path" timing constraints in the DCFIFO IP.  I updated the design to Quartus 17.1 which supports the lpm_hint “DISABLE_EMBEDDED_TIMING_CONSTRAINT=TRUE” and added the timing constraints recommended by the FIFO IP User Guide.  This improved things quite a bit, but I am still seeing data corruption on some units.

I read that the recommended set_max_skew constraint is apparently broken for asynchronous clock groups in Quartus versions up to 20.1 or so and I am now trying to migrate to Quartus 22.1std or 21.1.1.  With both of these, when I attempt to compile the design I get the error:

Error (16058): PLLs that use the x1 clock network and drive the same HSSI channel must be placed in the same transceiver bank. PLL "HD_Core_VS4KG2_V1v0_5AGXMA5_pipen1b:top|Tx_PLL_HD_5AGX:Tx_PLL_HD|av_xcvr_plls:tx_pll_hd_5agx_inst|pll[0].pll.cmu_pll.tx_pll" and PLL "HD_Core_VS4KG2_V1v0_5AGXMA5_pipen1b:top|Tx_PLL_SD_5AGX:Tx_PLL_SD|av_xcvr_plls:tx_pll_sd_5agx_inst|pll[0].pll.cmu_pll.tx_pll" use the x1 clock network and drive the same HSSI channel, however the PLLs are not assigned to the same transceiver bank. In the Assignment Editor, change the location assignment of the second specified PLL to location "CHANNELPLL_X132_Y53_N33" so the two PLLs are in the same transceiver bank. 

I have added location constraints and been unable to get past this error.  For a sanity check, I went back to the working 17.1 version, pulled the locations for my two Tx PLLs from the chip planner, created location constraints for the two PLLs, and recompiled to make sure everything still worked (it did).  I then took the design with location constraints and attempted to build with Quartus 21.1.1 and Quartus 22.1std and I continued to get error 16058.

The only thing I can find about this error is that it apparently was a problem with Quartus 17.1 that was fixed in 18.0: https://www.intel.com/content/www/us/en/support/programmable/articles/000082957.html?wapkw=16058 

This doesn't match what I see, as 17.1 is working for me but newer versions are failing.

And recommendations for how to get around this error, or how to properly constrain max. skew across async. clock domains with Quartus 17.1?

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Kshitij_Intel
Employee
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Hi,


Are you using SDI II IP with dynamic switch enable?


Can you please try with the latest version of Quartus 23.x.


Thank you

Kshitij Goel


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cdsteinkuehler
Beginner
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As mentioned, we are using our own IP for SDI but it supports "multi-rate" with each GXB Tx and Rx channel able to independently run at SD, HD, or 3G line rates.  This functionality is similar to the Altera SDI IP with dynamic switch enabled.

I am confused by your request to try with Quartus 23.x.  It appears Quartus 23.x is only available for "Quartus Pro", which does not support the Arria-V device family.  I will try with the current latest "Quartus Standard" 22.1.1 and report my results.

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cdsteinkuehler
Beginner
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Verified I get the same issue (Error 16058) using Quartus 22.1std.1 Build 917, which I believe is the latest version of Quartus that supports the Arria-V device family.

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Kshitij_Intel
Employee
1,939 Views

Hi,


Can you please share your project.


I will try to reproduce and resolve the issue.


Thank you

Kshitij Goel


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cdsteinkuehler
Beginner
1,926 Views

I have sent a Quartus archive file via private message.

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Kshitij_Intel
Employee
1,904 Views

Hi,


I do not received any file, you can share it here. There should not be any problem.


Thank you

Kshitij Goel


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cdsteinkuehler
Beginner
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This is a commercial design and I cannot post the archive to a public forum.  I sent you a private message via the forum, not an email.  Please check your forum messages (click the user icon in the upper-right corner and select "Messages") and let me know if you do not see the message.  The message appears in my "sent" folder on the forum addressed to your userid (https://community.intel.com/t5/user/viewprofilepage/user-id/213298).

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Kshitij_Intel
Employee
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Hi,


Thank you, I am able download the design. Now, I will try to compile it and replicate the issue.


Keep you posted.


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
1,769 Views

Hi,


I am able to replicate the issue, your design is compiling in Q18.0 without any errors but giving errors in later versions of Quartus.


I am looking into it.


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
1,699 Views

Hi,


I have escalated the case to the engineering department. Will keep you posted.


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
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Hi,


The HSSI team reviewing the issue. Will keep you posted.


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
1,578 Views

Hi,


As this case has been filed with intel premier support and it is in investigation. Also, the only workaround now is to use Q18.0std as it seems to be a bug in Q18.1std edition and later versions.


And to avoid duplication I am closing this case. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support here. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you

Kshitij Goel


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cdsteinkuehler
Beginner
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I am unable to access the supporttickets.intel.com site.  When I attempt to login, it accepts my email username, presents the azure login prompt which works with my new corporate SSO email and I get a prompt for the 2FA authentication code.  After entering this code, I am presented with a simple page that reads:

Salesforce

Single Sign-Error

We can't log you in because of an issue with single sign-on. Contact your Salesforce admin for help.

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cdsteinkuehler
Beginner
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