How to assign some HPS pins from arria10 Soc to FPGA control

[taojinyong]

Chip: Arria 10AS027E4F29E3SG
Software version: quartus18.1 standard 

For some reason I need to give some pins of the HPS to the FPGA to use, I set the pins of the HPS to none in Qsys, and then I use these pins in the fpga, and the compilation reports an error!

The error message is as follows：

Error (14996): The Fitter failed to find a legal placement for all periphery components
Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): The Fitter cannot place 217 pins.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): IO_B2A_L18_Y16_P, IO_B2A_L5_AF12_P, IO_B2A_L13_CLK0_AA16_N, IO_B3A_L24_AE5_P, IO_B2A_L13_CLK0_AB16_P and other 212 pins
Info (15647): These pins are in a group of 217 components with similar legality requirements
Error (16234): No legal location could be found out of 165 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended bidirectional pin locations available (134 locations affected)
Info (175029): H16. Already placed at this location: pin hps_io_hps_io_gpio_gpio1_io23
Info (175015): The I/O pad hps_io_hps_io_gpio_gpio1_io23 is constrained to the location PIN_H16 due to: User Location Constraints (PIN_H16)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): H17. Already placed at this location: pin hps_io_hps_io_gpio_gpio1_io22
Info (175015): The I/O pad hps_io_hps_io_gpio_gpio1_io22 is constrained to the location PIN_H17 due to: User Location Constraints (PIN_H17)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): J19. Already placed at this location: pin hps_io_hps_io_phery_spim0_MOSI
Info (175015): The I/O pad hps_io_hps_io_phery_spim0_MOSI is constrained to the location PIN_J19 due to: User Location Constraints (PIN_J19)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): J18. Already placed at this location: pin hps_io_hps_io_phery_spim0_CLK
Info (175015): The I/O pad hps_io_hps_io_phery_spim0_CLK is constrained to the location PIN_J18 due to: User Location Constraints (PIN_J18)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): K17. Already placed at this location: pin hps_io_hps_io_phery_spim0_SS0_N
Info (175015): The I/O pad hps_io_hps_io_phery_spim0_SS0_N is constrained to the location PIN_K17 due to: User Location Constraints (PIN_K17)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): J17. Already placed at this location: pin hps_io_hps_io_phery_spim0_MISO
Info (175015): The I/O pad hps_io_hps_io_phery_spim0_MISO is constrained to the location PIN_J17 due to: User Location Constraints (PIN_J17)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): E21. Already placed at this location: pin hps_io_hps_io_phery_emac0_MDC
Info (175015): The I/O pad hps_io_hps_io_phery_emac0_MDC is constrained to the location PIN_E21 due to: User Location Constraints (PIN_E21)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): D22. Already placed at this location: pin hps_io_hps_io_phery_emac0_MDIO
Info (175015): The I/O pad hps_io_hps_io_phery_emac0_MDIO is constrained to the location PIN_D22 due to: User Location Constraints (PIN_D22)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): E23. Already placed at this location: pin hps_io_hps_io_gpio_gpio1_io9
Info (175015): The I/O pad hps_io_hps_io_gpio_gpio1_io9 is constrained to the location PIN_E23 due to: User Location Constraints (PIN_E23)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): D23. Already placed at this location: pin hps_io_hps_io_gpio_gpio1_io8
Info (175015): The I/O pad hps_io_hps_io_gpio_gpio1_io8 is constrained to the location PIN_D23 due to: User Location Constraints (PIN_D23)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): C22. Already placed at this location: pin Flash_OE_N
Info (175015): The I/O pad Flash_OE_N is constrained to the location PIN_C22 due to: User Location Constraints (PIN_C22)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): C23. Already placed at this location: pin PWR_INT_VSEL
Info (175015): The I/O pad PWR_INT_VSEL is constrained to the location PIN_C23 due to: User Location Constraints (PIN_C23)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): and 122 more locations not displayed
Error (179008): Could not find enough available I/O pin locations that can be configured to use a VCCIO voltage of 1.8V (13 locations affected)
Info (175029): D9
Info (175029): A19
Info (175029): B20
Info (175029): E15
Info (175029): D15
Info (175029): D14
Info (175029): D13
Info (175029): C13
Info (175029): B15
Info (175029): B13
Info (175029): AH13
Info (175029): AG19
Info (175029): and 1 more location not displayed
Error (184016): There were not enough single-ended bidirectional pin locations available (10 locations affected)
Info (175029): A8
Info (175029): A9
Info (175029): AH10
Info (175029): AH11
Info (175029): Y17
Info (175029): AA17
Info (175029): AE21
Info (175029): AF21
Info (175029): AB23
Info (175029): AC23
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (8 locations affected)
Info (175029): F18
Info (175029): F17
Info (175029): H18
Info (175029): G18
Info (175029): G19
Info (175029): G20
Info (175029): F22
Info (175029): E22

[EBERLAZARE_I_Intel]

Hi,

You need to verify your pins for your device:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-10/10as027.pdf

Have you done pin assignment before?

[taojinyong]

Yes, I would like to control the I2C pins F22 and E22 of the HPS through FPGA logic. I first set Q3_7 and Q3_8 of the HPS to none in Qsys and then use the pins F22, E22 in the pin planner. Is this the right way to do it?

[EBERLAZARE_I_Intel]

Hi,

If that's the case, you can do a HPS Loan IO;

goto> Arria 10 HPS IP> Pin Mux and Peripheral Tab >in the Advance FPGA Placement > navigate to I2C and set the "Route to FPGA?" = Yes; any preferred IP Block.

[EBERLAZARE_I_Intel]

Hi,

Do you have any further update?

[EBERLAZARE_I_Intel]

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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