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Error fitter for PHY IP gen3

Moti
Employee
411 Views

Hi All,

 

I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, gen3 configuration.(Single lane)

the fitter reports the following error: 

Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
    Error (15744): In atom 'mfp_pcie_iip_wrap_inst|mfp_pcie_iip_device_inst|u_subsystem|fpga_phy|xcvr_native_s10_htile_0|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_pma_tx_cgb.inst_ct1_hssi_cr2_pma_tx_cgb'
    Error (15744): The settings must match one or more of these conditions: 
    Error (15744): ( pcie_gen != PCIE_GEN3_100MHZREF ) OR ( x1_clock_source_sel inside {FPLL_BOT_G1_G2,FPLL_BOT_G2_LCPLL_BOT_G3,FPLL_BOT_G2_LCPLL_TOP_G3,FPLL_TOP_G1_G2,FPLL_TOP_G2_LCPLL_BOT_G3,FPLL_TOP_G2_LCPLL_TOP_G3,LCPLL_BOT_G1_G2,LCPLL_TOP_G1_G2} )
    Error (15744): But the following assignments violate the above conditions: 
    Error (15744): input_select_x1 = LCPLL_BOT
    Error (15744): In atom 'mfp_pcie_iip_wrap_inst|mfp_pcie_iip_device_inst|u_subsystem|fpga_phy|xcvr_native_s10_htile_0|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_txpath_chnsequencer.inst_ct1_hssi_cr2_txpath_chnsequencer'
    Error (15744): The settings must match one or more of these conditions: 
    Error (15744): ( pcie_gen != PCIE_GEN3_100MHZREF ) OR ( x1_clock_source_sel inside {FPLL_BOT_G1_G2,FPLL_BOT_G2_LCPLL_BOT_G3,FPLL_BOT_G2_LCPLL_TOP_G3,FPLL_TOP_G1_G2,FPLL_TOP_G2_LCPLL_BOT_G3,FPLL_TOP_G2_LCPLL_TOP_G3,LCPLL_BOT_G1_G2,LCPLL_TOP_G1_G2} )
    Error (15744): But the following assignments violate the above conditions: 
    Error (15744): pcie_gen = PCIE_GEN3_100MHZREF
Error (12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted.
Error: ERROR: An error occurred during automatic periphery placement
Error: Quartus Prime Fitter was unsuccessful. 13 errors, 12 warnings
    Error: Peak virtual memory: 18550 megabytes
    Error: Processing ended: Mon Aug 23 15:02:09 2021
    Error: Elapsed time: 00:02:31
    Error: System process ID: 72940
Error (293001): Quartus Prime Full Compilation was unsuccessful. 15 errors, 13 warnings
Error (23035): Tcl error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error (23031): Evaluation of Tcl script /tmp/msamouch/Premier/mf_pcie_FPGA_PalmTree_fpga_21ww35_23_145243/rev_MX/premier_fpga_top_cons.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 21 errors, 13 warnings
    Error: Peak virtual memory: 1147 megabytes
    Error: Processing ended: Mon Aug 23 15:02:11 2021
    Error: Elapsed time: 00:05:12
    Error: System process ID: 71459

 the design have 4 IP :

1. ATX PLL - PCIe Gen3 single lane 100MHz , PLL output frequency is 2500MHz.

2. fPLL - PCIe Gen1 and Gen2 single lane 100MHz, with enable to PCIe output port for hclk of the PHY. 

3. Native PHY - PCIe PIPE Gen3x1 Native

4. Transceiver PHY Reset Controller

 

there are no error or warning at any IP wizard.

I will thank you for your help, can not find the problem

 

Thanks,

Moti

 

0 Kudos
1 Solution
Deshi_Intel
Moderator
335 Views

HI,


You are right. Your FPGA pin assignment setting is fine.


The problem is on your top level design connection. Below is the fix I made to your vqm design

  1. Fixed broken NativePHY (tx_serial_data) connection
  • I presume you want to connect to output port "DIFF100_PCIE_MOLEX_1KU12_PET" so I connect it back
  1. Fixed wrong clocking connection to NativePHY for PIPE GEN 3
  • fPLL tx_serial_clk should be connected to NativepHY tx_serial_clk0
    • ATX PLL tx_serial_clk should be connected to NativepHY tx_serial_clk1


You can also generate the example design directly from NativePHY IP to learn about the design connection

  • Goto NativePHY -> design example tab
    • change the fPLL default frequency from 125MHz back to 100MHz
    • Then click generate example design button


Thanks.


Regards,

dlim


View solution in original post

4 Replies
Deshi_Intel
Moderator
394 Views

Hi,


From the fitter error message, looks like it's complaining you are either using outdated Intel FPGA IP core or there is some invalid setting issue that caused fitter error later.


Typically Quartus fitter compilation error is either caused by wrong IP setting, wrong Quartus project top level design connection or wrong FPGA pin placement and pin setting issue.


Pls remove all sensitive FPGA core user design logic and just maintain the simplify design that just contains top level design with 4 Intel FPGA IP core that able to duplicate the fitter error.


Share your Quartus archived project *.qar then I can help to review your design to debug fitter error


Thanks.


Regards,

dlim


Moti
Employee
360 Views

Hi dlim,

 

thanks for your replay,  I remove all the project and compile only the 4 IP

 

I add the .qar file  ( please look for v2 )

( I want to mention that I succeed to compile PHY IP with gen1 AND gen2 with the same pins and constraints )

 

Thank you!

Moti

Deshi_Intel
Moderator
336 Views

Attached is the fitter error fixed design for your reference

Deshi_Intel
Moderator
336 Views

HI,


You are right. Your FPGA pin assignment setting is fine.


The problem is on your top level design connection. Below is the fix I made to your vqm design

  1. Fixed broken NativePHY (tx_serial_data) connection
  • I presume you want to connect to output port "DIFF100_PCIE_MOLEX_1KU12_PET" so I connect it back
  1. Fixed wrong clocking connection to NativePHY for PIPE GEN 3
  • fPLL tx_serial_clk should be connected to NativepHY tx_serial_clk0
    • ATX PLL tx_serial_clk should be connected to NativepHY tx_serial_clk1


You can also generate the example design directly from NativePHY IP to learn about the design connection

  • Goto NativePHY -> design example tab
    • change the fPLL default frequency from 125MHz back to 100MHz
    • Then click generate example design button


Thanks.


Regards,

dlim


Reply