Error in signal assignment with VHDL

Altera_Forum · ‎05-09-2012

I'm trying to create a simple register connected to a 8-width bidirectional bus. But when I read a value from this bus and write it back, some of these bits receive don't care value, while others are ok. I didn't understand that since I don't deal with these bits individually. Someone could help?

Below is the code:


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity reg is
    generic(
        MAX_COUNT: in natural := 8);
    port(data: inout std_logic_vector(MAX_COUNT-1 downto 0);
         incr,decr,lr,erd: in bit;
         clk: in std_logic);
end entity;
architecture behavioral of reg is
signal out_r: std_logic_vector(MAX_COUNT-1 downto 0);
begin
    process(clk)
    
    variable var: std_logic_vector(MAX_COUNT-1 downto 0);
    
    begin
        if rising_edge(clk) then
            if lr = '1' then
                var := data;
            end if;
            if incr = '1' then
                var := var+1; 
            end if;
            if decr = '1' then
                var := var-1; 
            end if;
            out_r <= var;
        end if;
    end process;
    
    process(clk,erd)
    begin   
       if rising_edge(clk) then
         if erd = '1' then
           data <= out_r;
         else
           data <= (others => 'Z');
         end if;
       end if;
    end process;
end architecture;

... and the image of the error in ModelSim:

&&&dl.dropbox.com/u/288645/erro_view.PNG&&&

Clearly we can see that some bits of the bus 'data' are don't care while others seem to have the correct value.

lr -> means load R

erd -> means enable R to bus

The others are easier. Thanks for the attention!

Altera_Forum · ‎05-10-2012

First things first. A 'X' is not a don't care for std_logic signals. A don't care is '-'.

What you see is two active bus drivers (one is your testbench and the other your design) are active at the same time and driving different values against each other.

Ok to explain what happens lets go through your simulation step by step:

time = 0 ns (start of simulation)

your testbench sets

incr = '1'

decr = '0'

lr = '0'

erd = '0'

data = 185

your logic does

out_r = "UUUUUUUU" (no assignment at declaration)

data = "UUUUUUUU" (no assignment at declaration) and the testbench drives 185 here is a conflict and you get "XXXXXXXX"

time = 5 ns (rising clock edge)

your logic does

out_r = "UUUUUUUU" + 1 = "XXXXXXXX"

data = "ZZZZZZZZ" therefore the testbench driver wins and you see 185

time = 10 ns (testbench changes)

your testbench sets

incr = '0'

decr = '1'

lr = '1'

erd = '0'

data = 114

time = 15 ns (rising clock edge)

your logic does

out_r = 114 - 1 = 113

data = "ZZZZZZZZ" therefore the testbench driver wins and you see 114

time = 20 ns (testbench changes)

your testbench sets

incr = '0'

decr = '0'

lr = '1'

erd = '1'

data = 101

time = 25 ns (rising clock edge)

your logic does

out_r = 101

data = previous out_r = 113 ("0111 0001") driving against 101 ("0110 0101") resulting in ("011X 0X01")

and so on.

Altera_Forum · ‎05-11-2012

Ok. So the solution is force just one value (against HiZ). Thus, in this case, when I put erd = '1', I need to have data = 'ZZZZZZZZ' in the testbench. Is that right?

Altera_Forum · ‎05-11-2012

yes, you could do that - but why do you need an inout bus at all? why cant you have separate data_in and data_out?

Altera_Forum · ‎05-11-2012

This is a small part of a microprocessor, then I have no choice.

Altera_Forum · ‎05-11-2012

I hope that your INOUT signal is going to the pins of the FPGA. Then there are no tri-state drivers inside the FPGA internal logic. Only the I/O's have tri-state drivers.

Altera_Forum · ‎05-11-2012

I know that. It's not going to be implemented on hardware (maybe in the future). The project is an assynchronous microprocessor only for learning purposes. Anyway, thank you all people.