Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
790 Views

Error in simulation due to unknown generated files in Modelsim

Hi all, 

I have made a Modelsim project and added 3 files to the project. After compilation, I have simulated pkt_enco_tb file as it is my testbench file. but I am getting errors as shown in attached image. 

Also, I have seen that after compilation, unknown files were generated like 'pkt_enco_tb_sv_unit' and 'pkt_encoder_sv_unit', I have attached an image for this. So I want to know that what is the significance of these files?:confused: 

and how to solve this error?.:confused: 

 

thank you.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
35 Views

Hi, 

 

The images are not clear, attach the transcript. 

Are you trying to simulate an individual IP / Own soc design? 

Can you share the design? 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

Hi, 

 

The images are not clear, attach the transcript. 

Are you trying to simulate an individual IP / Own soc design? 

Can you share the design? 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Hi, now you can see the images I have uploaded high-resolution images. 

And yes, I am trying to simulate my own design.
Altera_Forum
Honored Contributor I
35 Views

Hi, 

 

Can you share the files? 

To debug 

1. Can you try to simulate individual .v/.vhd file first?  

And find the file which causes the problem. Also, try to check the logic of it and its integration to the top file. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
35 Views

Hi,  

 

Somehow I got the solution by changing the order of files in the compilation. And keep the package files in the same folder where my testbench is. Below is my testbench code. 

I have come across another issue. I am using 2 package files, in the first package file, I have defined multiple byte structures. And using the first package I have defined structures of the group of bytes. So my case is, from testbench I have to write individual byte as per the first package and I have to read group of byte from second package. I am able to write in frist package but I did not get it from second package. So I want to know that is it possible ? if yes then How? and If no then what I can do for that?
Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

Hi, 

 

Can you share the files? 

To debug 

1. Can you try to simulate individual .v/.vhd file first?  

And find the file which causes the problem. Also, try to check the logic of it and its integration to the top file. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

I have solved this issue by the refreshing library in Modelsim before simulation.
Reply