Error with Virtual JTAG

Altera_Forum · ‎02-01-2012

Hi everyone,

I created a Virtual JTAG in MegaWizard Plug-In Manager and its instant below:

module counter (clock, my_counter);
	input clock;
	output  my_counter;
	reg  my_counter;
	
	always @ (posedge clock)
		if (load && e1dr) // decode logic: used to load the counter my_counter
			my_counter <= tmp_reg;
		else
			my_counter <= my_counter + 1;
	
	// Signals and registers declared for VJI instance
	wire tck, tdi;
	reg tdo;
	wire cdr, e1dr, e2dr, pdr, sdr, udr, uir, cir;
	wire  ir_in;
	// Instantiation of VJI
	Virtual_JTAG Virtual_JTAG_instant(
	.tdo (tdo),
	.tck (tck),
	.tdi (tdi),
	.tms(),
	.ir_in(ir_in),
	.ir_out(),
	.virtual_state_cdr (cdr),
	.virtual_state_e1dr(e1dr),
	.virtual_state_e2dr(e2dr),
	.virtual_state_pdr (pdr),
	.virtual_state_sdr (sdr),
	.virtual_state_udr (udr),
	.virtual_state_uir (uir),
	.virtual_state_cir (cir)
	);
	
	// Declaration of data register
	reg  tmp_reg;
	
	// Deocde Logic Block
	// Making some decode logic from ir_in output port of VJI
	wire load = ir_in && (~ir_in);
	
	// Bypass used to maintain the scan chain continuity for
	// tdi and tdo ports
	bypass_reg <= tdi;       // Error here
	
	// Data Register Block
	always @ (posedge tck)
	if ( load && sdr )
	tmp_reg <= {tdi, tmp_reg};
	
	// tdo Logic Block
	always @ (tmp_reg or bypass_reg)
	if(load)
	tdo <= tmp_reg;
	else
	tdo <= bypass_reg;
endmodule

and I got this error:

Error (10170): Verilog HDL syntax error at Virtual_JTAG_instant.v(46) near text "<=";  expecting ".", or "("

Can anyone help me solve this issue? :D

Altera_Forum · ‎02-01-2012

You're using VHDL syntax. Use Verilog syntax:


assign bypass_reg = tdi;

Cheers,

Dave