Essence of Time Constraint

[Altera_Forum]

Hi every body, 

I'm new in VHDL and I don't understand about essence of time constraint, .I 've tried to read many document, but they write much more detail in time constraint when I don't understand the essential principles. so I have some "stupid" questions about time constraint in VHDL. Please if you could answer me by you experiments. 1. Why have to constant? and how does the time constraint work? 2. Does It aply only for registers and clocks? what's about combintional logic, or group of logic? 3. How can I constraint the large project with many sub-entity, hundred of logic gates, registers.. 4. If I use the megafunction plugin, of which don't know the inner structure. (I don't know how many register, logic gate, clock are there and how do they connect...) So how can I constraint them? for example megacore: FFT, FIR, NCO... :confused::confused: Thanks you.

[Altera_Forum]

--- Quote Start ---   1. Why have to constant? and how does the time constraint work?   --- Quote End ---   VHDL describes what the logic does, however, it does not really define when and how fast it can do it, that is a function of the physical device. The same VHDL can run faster or slower depend on the FPGA you are using. If you have a particular frequency that you must operate at, then that is part of your FPGA selection process.    --- Quote Start ---   2. Does It aply only for registers and clocks? what's about combintional logic, or group of logic?   --- Quote End ---    It applies to both registered and combinatorial logic. However, in some cases you don't care about a combinatorial path, so you can apply a timing constraint that indicates you do not care about that particular path.    --- Quote Start ---   3. How can I constraint the large project with many sub-entity, hundred of logic gates, registers..   --- Quote End ---    Logic internal to the FPGA is generally constrained using a clock constraint.     --- Quote Start ---   4. If I use the megafunction plugin, of which don't know the inner structure. (I don't know how many register, logic gate, clock are there and how do they connect...) So how can I constraint them? for example megacore: FFT, FIR, NCO...   --- Quote End ---    An FFT, FIR, or NCO has registers on the input and output, so that component is essentially internal to the FPGA, and is covered by a clock constraint. If you send the output of an NCO over to a DAC to generate a sinusoid external to your FPGA, then the signals going between the FPGA and the DAC need to have I/O constraints applied. These constraints are determined by the external device, i.e., the DAC, its input registers have setup and hold timing requirements. You use a timing constraint to tell the synthesis tool what those constraints are, and it programs the FPGA I/O delay elements to meet those requirements.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi every body, I'm new in VHDL and I don't understand about essence of time constraint, .I 've tried to read many document, but they write much more detail in time constraint when I don't understand the essential principles.  --- Quote End ---   The essence of a time constraint is when one signal samples another signal. In order to sample the signal properly, the signal being sampled must be stable for some period of time before and after the sampling signal.   To put this a bit more concretely (and hopefully clearly) with an example, consider the simple flip flop. This device has an input 'D' and an input 'CLK'. The operation of the flip flop is that the input 'D' is sampled at the rising edge of 'CLK' and that sampled value is then held on the output 'Q' until the next rising edge of 'CLK'. Now think to yourself what this could mean. Does this mean that if 'D' switches from a 0 to a 1 logic level exactly 1 ns prior to the rising edge of 'CLK' should 'Q' become '0' or '1'? What if it switches 1 ps before? 1 fs before? Now also add on that 'D' switches back from '1' to a '0' exactly 1 ns (or 1 ps of 1 fs) after the rising edge of 'CLK'? Do you still expect 'Q' to be '1'? Ideally, yes, if 'D' was a '1' for 1 fs before the rising edge of 'CLK' and only stayed there until 1 ps after the rising edge of 'CLK' then the ideal flip flop would capture that and set 'Q' to 1.   Now welcome yourself to reality. Real devices will have some setup time requirements (i.e. the time prior to rising edge when 'D' must be stable) and hold time requirements (i.e. the time after the rising edge when 'D' must also be stable). Those times will not be measured in units of fs...unless you use a lot of them (like several thousand of them).   So now you have the basic principle. Whenever one signal (in this example 'CLK') samples another signal (in this example 'D') there will be setup and hold time requirements. Now maybe the function you're implementing has no sampling, it is pure combinatorial logic. No time constraints? Maybe...but maybe not. What if the output of your combinatorial logic leaves the device and goes to another device which samples it with some other signal. That other device may impose setup/hold time requirements on your output which could then translate into a propogation delay time requirement on your design.   At a minimum, any design will need to have the following timing requirements specified: - Setup time requirements for all inputs to the design that are sampled - Clock to output requirements for outputs of the design that will be sampled by an external device - Propogation delay requirements for any outputs that are combinatorial and where the system imposes a time constraint. These are not necessarily very common.   In a nutshell, that is where timing constraints come from. Dave also gave you some practical advice as well.   Kevin Jennings

[Altera_Forum]

Download the timequest.pdf I wrote in this thread. 

 http://www.alteraforum.com/forum/showthread.php?t=31457  There's some figures in there that should help, and cross-references to TimeQuest documentation. Rysc has a very nice guide on the Altera forum.  Cheers, Dave