Estimate total computation time in FPGA

[Altera_Forum]

Hi, 

I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at a specific instant. The code is executed properly and behaves according to my expectation. Now, I would like to find what will be the total computation time from the moment Iref sample is captured to the moment Vab is calculated as shown below. I used Modelsim to judge the computation delay in a simple multiplication (for example,Ip1 calculation as shown below) or division(for example,Ip calculation as shown below) but could not see any delay. Kindly give some advice how I can find the computation delay for each operation below?  entity Feedforwardv1 is  Port ( Iref : in unsigned(15 downto 0);  I : in STD_LOGIC;  Vab : out signed(19 downto 0)); end Feedforwardv1;   architecture Behavioral of Feedforwardv1 is   signal Irefprev,Ii1,Irefs : integer := 0; signal Ii2,Ip,Ip1,Iis,Ii : integer := 0; signal Ii3,Ii3prev: integer := 0; signal Kpz : integer := 245; signal Kiz1 : integer := 37941; signal Kiz2 : integer := 1190; begin    Ip1 <= Kpz*Irefs;  Ip <= Ip1/4096;  Ii1 <= Irefs - Irefprev;  Ii2 <= Kiz1*Ii1;  Iis <= Ii3prev+Ii2;  Ii <= Iis/2048;  Ii3 <= Kiz2*Ii;  Vab <= to_signed((Ip+Ii),20);   Process(I) begin  if(rising_edge(I)) then  Irefprev <= Irefs;  Irefs <= to_integer(Iref);  Ii3prev <= Ii3;  --Vab <= to_signed((Ip+Ii),20);  end if; end process;   end Behavioral;

[Altera_Forum]

Modelsim will not show you the delay, because there is 0 delay in the HDL because you didnt model any. HDL code does not have any delay because it only models a circuit. 

In the Max device, there will be a real delay, but because you have made an analogue circuit, this delay will vary depending on compilation routing, temperature, voltage and just random variations from chip to chip, so the delay is impossible to calculate.  If you used a synchronous circuit, you can work out the delay from the number of registers in the calculation pipeline.

[Altera_Forum]

I don't think that Tricky's (somewhat pedantic, although he is right in every point) answer won't be of much help ... 

 If your code simulates correctly, you can launch Quartus II and fit it in a real device. After compilation you can use Timequest to find the delay. I estimate that it will be quite high but less than say 200 ns. Which would give you a 5 MHz update frequency. I actually compiled you code and TimeQuest reported a tCO (clock to output) of 27 ns for a 10M08DAF484C8G device

[Altera_Forum]

The problem is timequest will only give the worst case using the given model. The actual delay can (and probably will) vary in real time, and likely to be less than timequest actually estimates. 

The only "safe" way to use logic like this, is to use a synchronous design.

[Altera_Forum]

What you want to say is: 

 although the input data is registered, the output value isn't. so the op has to realize that the transition after the i-pulse varies and probably will be a unstable (as not al bits will change at the same time) until the maximum delay given by timequest. To remedy this registering the output would be a good idea, but this comes with a penalty of one extra I-pulse delay. I agree this will need a different approach.

[Altera_Forum]

Hi Tricky and Josyb, 

Thank you both for replying. I am using 10M50DAF484C6GES. I am using a 50MHz (clock period=20ns ) clock. For me, if the total estimated delay from input to output is 200ns, it is good enough.  I also want to just estimate the delay and do not want an exact number for it. I am aware that the delay in the real implementation on FPGA will vary with voltage, temperature, routing, etc. I just wanted to learn how to estimate the delay for a particular code section. Also, I wanted to know how i can use TimeQuest to judge the delays. Is the delay from clock to output (tCO), which means clock to Vab output (in my code) 27ns? After synthesizing my design,when i open TimeQuest and click on Report all summaries, it shows in the summary(setup) that i have a negative clock slack. How to fix this? I am relatively new to FPGAs and QUARTUS II and do not know about all the tools but with the great support from Altera forums, I am learning fast.  Thank you again :)

[Altera_Forum]

You get a negative slack report when you don't have a Synopsys Design Constraints File(.sdc file) that describes the timing requirements. Quartus II then assumes a clock of 1 GHz (1 ns period) which obviously is never met.

[Altera_Forum]

Hi Josyb, 

 I have included .sdc file in my project and have added a clock of clock period=20ns (50Hz) but still i have a negative slack. Despite this,my code works fine as what i see from my signals in logic analyser. Also, I am now trying to estimate the propagation delay for my code by the number of operations in the calculation pipeline. Can you tell me what would be the delay of a single multiplication/division and a single addition in MAX 10 device. If i know these numbers, i will be able to estimate the total delay.  Regards, Misha

[Altera_Forum]

Division will be a much greater delay. 

Without compiling the circuit and looking in timequest, you will have no idea of the delay.

[Altera_Forum]

where to look for this delay in timequest? In which report?