Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 토론

porting a filelist to open a design in quartus

Altera_Forum
명예로운 기여자 II
1,841 조회수

hi, 

 

altera newbie here. how do i port a filelist (which has +200 verilog and/or .sv design files) into quartus to open a design? 

 

is there an option where I can simply point to the filelist through Quartus GUI and the files are parsed and the heirarchy is shown? 

 

also, in quartus, can we see the file heirarchy before we doing a compile (to see if the files have been picked properly)? 

 

thanks in advance for the help. 

 

i am using quartus II version 15.0 

 

z.
0 포인트
2 응답
Altera_Forum
명예로운 기여자 II
885 조회수

I doubt it you can just put a collection of files and get hierarchy. 

you need a project file first since hierarchy is determined after compilation.
0 포인트
Altera_Forum
명예로운 기여자 II
885 조회수

As long as you know what the top level entity is called then you can just add all your source files to a Quartus project and run Analysis & Synthesis. 

 

1) Create a Quartus project. 

2) Under 'Project' -> ''Add/Remove Files in Project...'. 

3) Add all the source files you want. 

4) Within the same 'Settings' window select the 'General' category. 

5) Enter the 'Top-level entity:' accordingly. 

6) Run Analysis & Synthesis. 

 

Quartus will analyse all the files, find the top entity you specified and work out the hierarchy from there - ignoring any entities/files it doesn't need. You will then be able to view the hierarchy Quartus finds in the 'Project Navigator'. 

 

Cheers, 

Alex
0 포인트
응답