Ethernet suggestion

[ochiang]

Hi,

I am using a Cyclone V SoC FPGA and I would like to inquire about the feasibility of using this component for Ethernet communication at speeds of at least 2.5Gbps.

I am open to using either the HPS or the FPGA Fabric.

I would appreciate any related suggestions, peripheral components, simple architectures, or design examples that you can provide for reference.

Thank you very much.

[Jeet14]

Hi,

Unfortunately, we don't have support for 2.5G ethernet support from the HPS or FPGA side on Cyclone V SX device.

On Cyclone V SX SoC FPGA, at HPS side you can use ethernet only 10/100/1000 Mbps.

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/ethernet-media-access-controller.html

But in Cyclone 10 GX device, you can use the 2.5G ethernet.

https://www.intel.com/content/www/us/en/docs/programmable/683054/20-1/about-the-1g-2-5g-5g-10g-multi-rate.html

Regards

Tiwari

[ochiang]

Hi Jeet14,

thank you for your reply,

I saw in the documentation that both the Cyclone V Transceiver Native PHY IP Core and the Custom PHY IP Core support GIGE-2.5Gbps PCS. Can't these be used to implement 2.5Gbps Ethernet?

[Jeet14]

Hi,

Please refer the below link for the ethernet IP support on Cyclone V SX device.

Find Intel® FPGA Intellectual Property (IP) Cores

This link shows the support for ethernet IP 1G and 10G on Cyclone V but not the 2.5G ethernet IP.

Regards

Tiwari

[ochiang]

Hi Tiwari,

Thank you for your reply,

I instantiated a Native PHY IP within the Cyclone V SX and used the IP Library to set GIGE-2.5Gbps. I can see that the IP sets the Data rate to 3125Mbps on the PMA configuration page (as shown in the image). Doesn't this indicate that the Cyclone V SX is capable of 2.5Gbps Ethernet?

Thank you very much.

[Jeet14]

Hi,

Yes this Cyclone V Transceiver native phy have this configuration but we don't have the ethernet IP from us on cyclone V which can give you 2.5G speed.

example- We have Multirate ethernet IP which supports Arria V device. https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/10g-multirate-ethernet-phy.html

For this you can use the third party IP or you can build your own IP for this.

Regards

Tiwari

[ochiang]

Hi Tiwari,

thank you for your reply,

So, can I implement a simple Ethernet frame processing (MAC Layer) in RTL, then connect the RTL to the Native PHY, and use an external PHY component like SGMII+ (e.g., GPY211) to achieve 2.5G Ethernet? Is this feasible?

Thank you very much.

[Jeet14]

Hi,

Yes, you need to write RTL logic for MAC+PCS & MDIO logic as well for external PHY's then you can directly connect it with XCVR Native PHY 2.5G.

Regards

Tiwari

[ochiang]

Hi Tiwari,

I am very grateful for your information; it has been very helpful to me.

However, I have some additional questions. There is already a Standard PCS within the Native PHY. When I select GigE 2.5G, it sets up to enable PCS 8b/10b. How is this different from the PCS you mentioned? Specifically, what additional PCS functionality do I need to implement? Could you provide some hints?

Are you referring to handling things like Ordered-sets?

Thank you very much.

[Jeet14]

Hi,

You need to define the interface like RX/TX 16-bit GMII in the RTL MAC and connect it to PCS 8b/10b.

Regards

Tiwari

[Jeet14]

Hi,

Please let me know if you have any other query on this.

Regards

Tiwari

[ochiang]

Hi Tiwari,

Thank you very much for your help. I will continue to research some items related to PCS. Thank you.

[Jeet14]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Tiwari