I have been trying to find a way to generate the programming file that is used to configure HardCopy Series devices. The basic logic elements of HardCopy devices is HCells (equivalent to ALMs in FPGAs), they are "rewired" based on the type of the implemented design and constrains.
Quartus provides the option to assign a companion FPGA device that can be used for testing, a programming file is generated for the companion device. However, I would like to analyze the final connection layout of the configurable part of the HardCopy device.
Is there an option in Quartus that allows me to generate an HCell-level configuration file?