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Valued Contributor III
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Extremelly confused in Cyclone V Transceivers reconfiguration

Hello dear friends. 

 

I have a Cyclone V 5CSXFC6D6F31C8 chip. On PCB board, all 9 transceivers are connected to periphery and 1 reference clock (REFCLK1L) are connected to reference clock source (other reference clocks are grounded). 

I want to build 9-channel transceiver that have reconfigurable speed (700/2800Mbps) on each channel independently on other channels. 

So i can build project with single reconfigurable channel, but i totally cant build 9-channels reconfigurable project. 

 

I read Transceiver User Guide, AN676 and tons of other information but can't build all channels are reconfigurable. 

I try these solutions: 

1. 9-channel transceiver with bonded/non-bonded internal TXPLL's - cant compile. 

2. 9-channel transceiver with bonded/non-bonded external TXPLL's (two Transceiver PLL) - cant compile. 

3. 9-channel transceiver with bonded/non-bonded external TXPLL's (two Fractional PLL) - cant compile. 

4. 9-channel transceiver with bonded/non-bonded external TXPLL's (Mixed Transceiver and Fractional PLL) - cant compile. 

At all variants Quartus compilation fails with errors. 

 

Please help me because i'm critically confused with it... 

Lot of thanks to all. 

 

p.s.: i attach my test project that fails. 

https://alteraforum.com/forum/attachment.php?attachmentid=13904&stc=1
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Valued Contributor III
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So, i continue experiments: any configurations with channels count 2 and more will fails at fitter stage. 

I try also external FPLL with 2-clock output, but it fails too because transceiver core need to be clocked from PHOUT output that drives only one clock. 

 

Can anybody say me what i do wrong?
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Valued Contributor III
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Hmmm... Nobody have same problems?

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Valued Contributor III
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So i return to this problem after some time. 

 

Now i'm stay off in this point: 

 

The project consist of these modules: 

- Separate FPLL with it own PLL Reconfigurator IP. 

- Transceiver in external PLL mode (i use 2 TX PLL's - TXPLL0=622.08 and TXPLL1=2488.32, bonding xN used). 

- Base speed of transceiver is 622.08 (and 322.04 for FPLL respectively). 

- Transceiver reconfiguration IP (number of channels same as number of channels in transceiver, MIF reconfiguration enabled). 

 

What results i have: 

For channels count from 1 to 6 compilation are successful. 

For channels count from 7 to 8 compilation fails with errors: 

Info (170193): Fitter routing operations beginning Error (170084): Can't route signal "xcvr:inst3|altera_xcvr_native_av:xcvr_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts.av_tx_pma_ch_inst|tx_pma_ch.int_wire_clk" to atom "xcvr:inst3|altera_xcvr_native_av:xcvr_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts.av_tx_pma_ch_inst|tx_pma_ch.tx_cgb" Error (170084): Can't route signal "xcvr:inst3|altera_xcvr_native_av:xcvr_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts.av_tx_pma_ch_inst|tx_pma_ch.int_wire_clk" to atom "xcvr:inst3|altera_xcvr_native_av:xcvr_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts.av_tx_pma_ch_inst|tx_pma_ch.tx_cgb" Info (170194): Fitter routing operations ending: elapsed time is 00:00:01  

 

 

Can anybody help me with it?
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